From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 90644C433EF for ; Fri, 6 May 2022 00:12:17 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4KvWGS0sLRz3fgn for ; Fri, 6 May 2022 10:12:16 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=LWHeddeJ; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=LWHeddeJ; dkim-atps=neutral Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4KvVzR4WZ1z3bym for ; Fri, 6 May 2022 09:59:15 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651795155; x=1683331155; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=L3Ao7/ADM/27W4au5Ct5JCZDRw2G77dHHek57JRUTvg=; b=LWHeddeJ/0nKv8ODMXOJTYsFcc0b288EaOjQEoudhwQCvah2A+K2ntty AokRkDATvqFTqHLssrX9ygUK+ivqynnZ3MTa8Xm1dlzc+iWLEiPnsPfS7 r8ZVLPWGlzIC6Y8vG5erHS5GNfG0XEdHxEz0Ix4VEoychT5K2hcmGRl+e lm7vQreT0Ou0DGBC0yH7US/ayAbTbbx7/kNDcZkmKS7YYpz7JDU1fJHuO AEeoPPiZBQs3jgRWt3wqchdJsN3PK+UVRxS06UMStW3RkAKkDps5B4Epo vklVCOWJplmx24GS44s3dQChybdMMNOE3goCoIw7vxoeuU6hy8U+kwHus w==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="268437330" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="268437330" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 16:57:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="694914422" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga004.jf.intel.com with ESMTP; 05 May 2022 16:57:53 -0700 From: Ricardo Neri To: Thomas Gleixner , x86@kernel.org Subject: [PATCH v6 21/29] x86/nmi: Add an NMI_WATCHDOG NMI handler category Date: Thu, 5 May 2022 17:00:00 -0700 Message-Id: <20220506000008.30892-22-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com> References: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , linuxppc-dev@lists.ozlabs.org, Joerg Roedel , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Tony Luck , Nicholas Piggin , Suravee Suthikulpanit , Ricardo Neri , Andrew Morton , David Woodhouse , Lu Baolu Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Add a NMI_WATCHDOG as a new category of NMI handler. This new category is to be used with the HPET-based hardlockup detector. This detector does not have a direct way of checking if the HPET timer is the source of the NMI. Instead, it indirectly estimates it using the time-stamp counter. Therefore, we may have false-positives in case another NMI occurs within the estimated time window. For this reason, we want the handler of the detector to be called after all the NMI_LOCAL handlers. A simple way of achieving this with a new NMI handler category. Cc: Andi Kleen Cc: Andrew Morton Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Cc: x86@kernel.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v5: * Updated to call instrumentation_end() as per f051f6979550 ("x86/nmi: Protect NMI entry against instrumentation") Changes since v4: * None Changes since v3: * None Changes since v2: * Introduced this patch. Changes since v1: * N/A --- arch/x86/include/asm/nmi.h | 1 + arch/x86/kernel/nmi.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index 1cb9c17a4cb4..4a0d5b562c91 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h @@ -28,6 +28,7 @@ enum { NMI_UNKNOWN, NMI_SERR, NMI_IO_CHECK, + NMI_WATCHDOG, NMI_MAX }; diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index e73f7df362f5..fde387e0812a 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -61,6 +61,10 @@ static struct nmi_desc nmi_desc[NMI_MAX] = .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[3].lock), .head = LIST_HEAD_INIT(nmi_desc[3].head), }, + { + .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[4].lock), + .head = LIST_HEAD_INIT(nmi_desc[4].head), + }, }; @@ -168,6 +172,8 @@ int __register_nmi_handler(unsigned int type, struct nmiaction *action) */ WARN_ON_ONCE(type == NMI_SERR && !list_empty(&desc->head)); WARN_ON_ONCE(type == NMI_IO_CHECK && !list_empty(&desc->head)); + WARN_ON_ONCE(type == NMI_WATCHDOG && !list_empty(&desc->head)); + /* * some handlers need to be executed first otherwise a fake @@ -379,6 +385,10 @@ static noinstr void default_do_nmi(struct pt_regs *regs) } raw_spin_unlock(&nmi_reason_lock); + handled = nmi_handle(NMI_WATCHDOG, regs); + if (handled == NMI_HANDLED) + goto out; + /* * Only one NMI can be latched at a time. To handle * this we may process multiple nmi handlers at once to -- 2.17.1