From: Kajol Jain <kjain@linux.ibm.com>
To: mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org
Cc: kjain@linux.ibm.com, atrajeev@linux.vnet.ibm.com,
maddy@linux.ibm.com, disgoel@linux.vnet.ibm.com,
rnsastry@linux.ibm.com
Subject: [PATCH 01/35] selftest/powerpc/pmu: Add mask/shift bits for extracting threshold compare field
Date: Fri, 6 May 2022 14:15:10 +0530 [thread overview]
Message-ID: <20220506084544.56527-2-kjain@linux.ibm.com> (raw)
In-Reply-To: <20220506084544.56527-1-kjain@linux.ibm.com>
In power10, threshold compare field is not part of the raw
event code and provided via event attribute config1.
Hence add the mask and shift bits based on event attribute
config1, to extract the threshold compare value for power10
Also add a new function called get_thresh_cmp_val to compute
and return the threshold compare field for a given platform,
since incase of power10, threshold compare value provided
is decimal.
Signed-off-by: Kajol Jain<kjain@linux.ibm.com>
---
.../powerpc/pmu/sampling_tests/misc.c | 44 +++++++++++++++++++
.../powerpc/pmu/sampling_tests/misc.h | 1 +
2 files changed, 45 insertions(+)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
index fca054bbc094..1afcd98f6036 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
@@ -60,6 +60,8 @@ static void init_ev_encodes(void)
switch (pvr) {
case POWER10:
+ ev_mask_thd_cmp = 0x3ffff;
+ ev_shift_thd_cmp = 0;
ev_mask_rsq = 1;
ev_shift_rsq = 9;
ev_mask_comb = 3;
@@ -410,3 +412,45 @@ u64 get_reg_value(u64 *intr_regs, char *register_name)
return *(intr_regs + register_bit_position);
}
+
+int get_thresh_cmp_val(struct event event)
+{
+ int exp = 0;
+ u64 result = 0;
+ u64 value;
+
+ if (!have_hwcap2(PPC_FEATURE2_ARCH_3_1))
+ return EV_CODE_EXTRACT(event.attr.config, thd_cmp);
+
+ value = EV_CODE_EXTRACT(event.attr.config1, thd_cmp);
+
+ if (!value)
+ return value;
+
+ /*
+ * Incase of P10, thresh_cmp value is not part of raw event code
+ * and provided via attr.config1 parameter. To program threshold in MMCRA,
+ * take a 18 bit number N and shift right 2 places and increment
+ * the exponent E by 1 until the upper 10 bits of N are zero.
+ * Write E to the threshold exponent and write the lower 8 bits of N
+ * to the threshold mantissa.
+ * The max threshold that can be written is 261120.
+ */
+ if (value > 261120)
+ value = 261120;
+ while ((64 - __builtin_clzl(value)) > 8) {
+ exp++;
+ value >>= 2;
+ }
+
+ /*
+ * Note that it is invalid to write a mantissa with the
+ * upper 2 bits of mantissa being zero, unless the
+ * exponent is also zero.
+ */
+ if (!(value & 0xC0) && exp)
+ result = -1;
+ else
+ result = (exp << 8) | value;
+ return result;
+}
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index 7675f3177725..078120883fde 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -52,6 +52,7 @@ void *__event_read_samples(void *sample_buff, size_t *size, u64 *sample_count);
int collect_samples(void *sample_buff);
u64 *get_intr_regs(struct event *event, void *sample_buff);
u64 get_reg_value(u64 *intr_regs, char *register_name);
+int get_thresh_cmp_val(struct event event);
static inline int get_mmcr0_fc56(u64 mmcr0, int pmc)
{
--
2.31.1
next prev parent reply other threads:[~2022-05-06 8:47 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-06 8:45 [PATCH 00/35] Add group constraints and event code test as part of selftest Kajol Jain
2022-05-06 8:45 ` Kajol Jain [this message]
2022-05-06 8:45 ` [PATCH 02/35] testing/selftests/powerpc: Add support to fetch "platform" and "base platform" from auxv to detect platform Kajol Jain
2022-05-06 8:45 ` [PATCH 03/35] selftest/powerpc/pmu: Add interface test for mmcra_thresh_cmp fields Kajol Jain
2022-05-06 8:45 ` [PATCH 04/35] selftest/powerpc/pmu: Add support for branch sampling in get_intr_regs function Kajol Jain
2022-05-06 8:45 ` [PATCH 05/35] selftest/powerpc/pmu: Add interface test for mmcra_ifm field of indirect call type Kajol Jain
2022-05-06 8:45 ` [PATCH 06/35] selftest/powerpc/pmu: Add interface test for mmcra_ifm field for any branch type Kajol Jain
2022-05-06 8:45 ` [PATCH 07/35] selftest/powerpc/pmu: Add interface test for mmcra_ifm field for conditional " Kajol Jain
2022-05-06 8:45 ` [PATCH 08/35] selftest/powerpc/pmu: Add interface test for bhrb disable field Kajol Jain
2022-05-06 8:45 ` [PATCH 09/35] selftest/powerpc/pmu: Refactor the platform check and add macros to find array size/PVR Kajol Jain
2022-05-06 8:45 ` [PATCH 10/35] selftest/powerpc/pmu: Add selftest to check branch stack enablement will not crash on any platforms Kajol Jain
2022-05-06 8:45 ` [PATCH 11/35] selftest/powerpc/pmu: Add selftest to check PERF_SAMPLE_REGS_INTR option " Kajol Jain
2022-05-06 8:45 ` [PATCH 12/35] selftest/powerpc/pmu: Add selftest for checking valid and invalid bhrb filter maps Kajol Jain
2022-05-06 8:45 ` [PATCH 13/35] selftest/powerpc/pmu: Add selftest for mmcr1 pmcxsel/unit/cache fields Kajol Jain
2022-05-06 8:45 ` [PATCH 14/35] selftest/powerpc/pmu: Add interface test for bhrb disable field for non-branch samples Kajol Jain
2022-05-06 8:45 ` [PATCH 15/35] selftest/powerpc/pmu: Add support for perf event code tests Kajol Jain
2022-05-06 8:45 ` [PATCH 16/35] selftest/powerpc/pmu: Add selftest for group constraint check for PMC5 and PMC6 Kajol Jain
2022-05-06 8:45 ` [PATCH 17/35] selftest/powerpc/pmu: Add selftest to check PMC5/6 is excluded from some constraint checks Kajol Jain
2022-05-06 8:45 ` [PATCH 18/35] selftest/powerpc/pmu: Add selftest to check constraint for number of counters in use Kajol Jain
2022-05-06 8:45 ` [PATCH 19/35] selftest/powerpc/pmu: Add selftest for group constraint check when using same PMC Kajol Jain
2022-05-06 8:45 ` [PATCH 20/35] selftest/powerpc/pmu: Add selftest for group constraint check for radix_scope_qual field Kajol Jain
2022-05-06 8:45 ` [PATCH 21/35] selftest/powerpc/pmu: Add selftest for group constraint for MMCRA Sampling Mode field Kajol Jain
2022-05-06 8:45 ` [PATCH 22/35] selftest/powerpc/pmu: Add selftest for group constraint check MMCRA sample bits Kajol Jain
2022-05-06 8:45 ` [PATCH 23/35] selftest/powerpc/pmu: Add selftest for checking invalid bits in event code Kajol Jain
2022-05-06 8:45 ` [PATCH 24/35] selftest/powerpc/pmu: Add selftest for reserved bit check for MMCRA thresh_ctl field Kajol Jain
2022-05-06 8:45 ` [PATCH 25/35] selftest/powerpc/pmu: Add selftest for blacklist events check in power9 Kajol Jain
2022-05-06 8:45 ` [PATCH 26/35] selftest/powerpc/pmu: Add selftest for event alternatives for power9 Kajol Jain
2022-05-06 8:45 ` [PATCH 27/35] selftest/powerpc/pmu: Add selftest for event alternatives for power10 Kajol Jain
2022-05-06 8:45 ` [PATCH 28/35] selftest/powerpc/pmu: Add selftest for PERF_TYPE_HARDWARE events valid check Kajol Jain
2022-05-06 8:45 ` [PATCH 29/35] selftest/powerpc/pmu: Add selftest for group constraint check for MMCR0 l2l3_sel bits Kajol Jain
2022-05-06 8:45 ` [PATCH 30/35] selftest/powerpc/pmu: Add selftest for group constraint check for MMCR1 cache bits Kajol Jain
2022-05-06 8:45 ` [PATCH 31/35] selftest/powerpc/pmu: Add selftest for group constraint check for MMCRA thresh_cmp field Kajol Jain
2022-05-06 8:45 ` [PATCH 32/35] selftest/powerpc/pmu: Add selftest for group constraint for unit and pmc field in p9 Kajol Jain
2022-05-06 8:45 ` [PATCH 33/35] selftest/powerpc/pmu: Add selftest for group constraint check for MMCRA thresh_ctl field Kajol Jain
2022-05-06 8:45 ` [PATCH 34/35] selftest/powerpc/pmu: Add selftest for group constraint check for MMCRA thresh_sel field Kajol Jain
2022-05-06 8:45 ` [PATCH 35/35] selftest/powerpc/pmu: Add test for hardware cache events Kajol Jain
2022-05-18 13:23 ` [PATCH 00/35] Add group constraints and event code test as part of selftest Michael Ellerman
2022-05-19 16:26 ` Athira Rajeev
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