From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59E1BC433F5 for ; Wed, 11 May 2022 23:41:34 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4KzBJD6Bzwz3bs4 for ; Thu, 12 May 2022 09:41:32 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=Re+nssaR; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kernel.org (client-ip=145.40.68.75; helo=ams.source.kernel.org; envelope-from=helgaas@kernel.org; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=Re+nssaR; dkim-atps=neutral Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4KzBH30ctfz3bxH for ; Thu, 12 May 2022 09:40:31 +1000 (AEST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A8EA6B82642; Wed, 11 May 2022 23:40:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3DA7BC340EE; Wed, 11 May 2022 23:40:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652312426; bh=BcJUboTaUZoL2am5X6SCUpWDDgK1oDr15p8F92dFBuk=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=Re+nssaRjnexpOCMoYquJSp2d4EXRkZ9id1SfJXDfgOm7quJkAH/GX7EfWXjz1pwQ PxuG+scSUVN1f4jUQITeJGass9vxshOdI90aUk5+B42Orkv7em+IrzeNzxja8GCDQ2 qcrxBfkYllmfGFr4VdXKAmDOEgXJKTGRmxH5VKLjQ4quuahihsYCl/m7PkOXbPCWGC ro9WYcopCpPItPSlLhnE5fPLx/SyATbMAFpm5AeNKV/dypO2QPZzNC7U00A7KTehPx fM0qrMqbds2rMVX8mN21jJYczHYh3J904YufGJOsMoox/UMBC2lxmrT96tlMzPr40f EUzEGzwduIotw== Date: Wed, 11 May 2022 18:40:24 -0500 From: Bjorn Helgaas To: Kuppuswamy Sathyanarayanan Subject: Re: [PATCH v3] PCI/AER: Handle Multi UnCorrectable/Correctable errors properly Message-ID: <20220511234024.GA831116@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220418150237.1021519-1-sathyanarayanan.kuppuswamy@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Oliver OHalloran , Bjorn Helgaas , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, Apr 18, 2022 at 03:02:37PM +0000, Kuppuswamy Sathyanarayanan wrote: > Currently the aer_irq() handler returns IRQ_NONE for cases without bits > PCI_ERR_ROOT_UNCOR_RCV or PCI_ERR_ROOT_COR_RCV are set. But this > assumption is incorrect. > > Consider a scenario where aer_irq() is triggered for a correctable > error, and while we process the error and before we clear the error > status in "Root Error Status" register, if the same kind of error > is triggered again, since aer_irq() only clears events it saw, the > multi-bit error is left in tact. This will cause the interrupt to fire > again, resulting in entering aer_irq() with just the multi-bit error > logged in the "Root Error Status" register. > > Repeated AER recovery test has revealed this condition does happen > and this prevents any new interrupt from being triggered. Allow to > process interrupt even if only multi-correctable (BIT 1) or > multi-uncorrectable bit (BIT 3) is set. > > Also note that, for cases with only multi-bit error is set, since this > is not the first occurrence of the error, PCI_ERR_ROOT_ERR_SRC may have > zero or some junk value. So we cannot cleanly process this error > information using aer_isr_one_error(). All we are attempting with this > fix is to make sure error interrupt processing can continue in this > scenario. > > This error can be reproduced by making following changes to the > aer_irq() function and by executing the given test commands. > > static irqreturn_t aer_irq(int irq, void *context) > struct aer_err_source e_src = {}; > > pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, > &e_src.status); > + pci_dbg(pdev->port, "Root Error Status: %04x\n", > + e_src.status); > if (!(e_src.status & AER_ERR_STATUS_MASK)) Do you mean if (!(e_src.status & (PCI_ERR_ROOT_UNCOR_RCV|PCI_ERR_ROOT_COR_RCV))) here? AER_ERR_STATUS_MASK would be after this fix. > return IRQ_NONE; > > + mdelay(5000);