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Thu, 13 Oct 2022 17:17:44 -0700 (PDT) Received: from server.roeck-us.net ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id e24-20020a656798000000b00454f8a8cc24sm281217pgr.12.2022.10.13.17.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Oct 2022 17:17:43 -0700 (PDT) Date: Thu, 13 Oct 2022 17:17:42 -0700 From: Guenter Roeck To: Nicholas Piggin Subject: Re: [PATCH 1/3] powerpc/64s: Disable preemption in hash lazy mmu mode Message-ID: <20221014001742.GA412544@roeck-us.net> References: <20221013151647.1857994-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221013151647.1857994-1-npiggin@gmail.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Fri, Oct 14, 2022 at 01:16:45AM +1000, Nicholas Piggin wrote: > apply_to_page_range on kernel pages does not disable preemption, which > is a requirement for hash's lazy mmu mode, which keeps track of the > TLBs to flush with a per-cpu array. > > Reported-by: Guenter Roeck > Signed-off-by: Nicholas Piggin Tested-by: Guenter Roeck > --- > arch/powerpc/include/asm/book3s/64/tlbflush-hash.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h b/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h > index fab8332fe1ad..751921f6db46 100644 > --- a/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h > +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h > @@ -32,6 +32,11 @@ static inline void arch_enter_lazy_mmu_mode(void) > > if (radix_enabled()) > return; > + /* > + * apply_to_page_range can call us this preempt enabled when > + * operating on kernel page tables. > + */ > + preempt_disable(); > batch = this_cpu_ptr(&ppc64_tlb_batch); > batch->active = 1; > } > @@ -47,6 +52,7 @@ static inline void arch_leave_lazy_mmu_mode(void) > if (batch->index) > __flush_tlb_pending(batch); > batch->active = 0; > + preempt_enable(); > } > > #define arch_flush_lazy_mmu_mode() do {} while (0) > -- > 2.37.2 >