* [PATCH 1/3] crypto: powerpc - Use address generation helper for asm
2023-02-03 11:38 [PATCH 0/3] powerpc: prepare for pcrel addressing patches Nicholas Piggin
@ 2023-02-03 11:38 ` Nicholas Piggin
2023-02-03 11:38 ` [PATCH 2/3] powerpc/64s: Refactor initialisation after prom Nicholas Piggin
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Nicholas Piggin @ 2023-02-03 11:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
Replace open-coded toc-relative address calculation with helper macros,
commit dab3b8f4fd09 ("powerpc/64: asm use consistent global variable
declaration and access") made similar conversions already but missed
this one.
This allows data addressing model to be changed more easily.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/crypto/crc32-vpmsum_core.S | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/crypto/crc32-vpmsum_core.S b/arch/powerpc/crypto/crc32-vpmsum_core.S
index a16a717c809c..b0f87f595b26 100644
--- a/arch/powerpc/crypto/crc32-vpmsum_core.S
+++ b/arch/powerpc/crypto/crc32-vpmsum_core.S
@@ -113,9 +113,7 @@ FUNC_START(CRC_FUNCTION_NAME)
#endif
#ifdef BYTESWAP_DATA
- addis r3,r2,.byteswap_constant@toc@ha
- addi r3,r3,.byteswap_constant@toc@l
-
+ LOAD_REG_ADDR(r3, .byteswap_constant)
lvx byteswap,0,r3
addi r3,r3,16
#endif
@@ -150,8 +148,7 @@ FUNC_START(CRC_FUNCTION_NAME)
addi r7,r7,-1
mtctr r7
- addis r3,r2,.constants@toc@ha
- addi r3,r3,.constants@toc@l
+ LOAD_REG_ADDR(r3, .constants)
/* Find the start of our constants */
add r3,r3,r8
@@ -506,8 +503,7 @@ FUNC_START(CRC_FUNCTION_NAME)
.Lbarrett_reduction:
/* Barrett constants */
- addis r3,r2,.barrett_constants@toc@ha
- addi r3,r3,.barrett_constants@toc@l
+ LOAD_REG_ADDR(r3, .barrett_constants)
lvx const1,0,r3
lvx const2,off16,r3
@@ -610,8 +606,7 @@ FUNC_START(CRC_FUNCTION_NAME)
cmpdi r5,0
beq .Lzero
- addis r3,r2,.short_constants@toc@ha
- addi r3,r3,.short_constants@toc@l
+ LOAD_REG_ADDR(r3, .short_constants)
/* Calculate where in the constant table we need to start */
subfic r6,r5,256
--
2.37.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/3] powerpc/64s: Refactor initialisation after prom
2023-02-03 11:38 [PATCH 0/3] powerpc: prepare for pcrel addressing patches Nicholas Piggin
2023-02-03 11:38 ` [PATCH 1/3] crypto: powerpc - Use address generation helper for asm Nicholas Piggin
@ 2023-02-03 11:38 ` Nicholas Piggin
2023-02-03 11:38 ` [PATCH 3/3] powerpc/64e: Simplify address calculation in secondary hold loop Nicholas Piggin
2023-02-15 12:40 ` [PATCH 0/3] powerpc: prepare for pcrel addressing patches Michael Ellerman
3 siblings, 0 replies; 5+ messages in thread
From: Nicholas Piggin @ 2023-02-03 11:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
Move some basic Book3S initialisation after prom to a function similar
to what Book3E looks like. Book3E returns from this function at the
virtual address mapping, and Book3S will do the same in a later change,
so making them look similar helps with that.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/head_64.S | 44 ++++++++++++++++++++---------------
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 7558ba4eb864..5af2e473b195 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -475,8 +475,30 @@ SYM_FUNC_START_LOCAL(__mmu_off)
rfid
b . /* prevent speculative execution */
SYM_FUNC_END(__mmu_off)
-#endif
+start_initialization_book3s:
+ mflr r25
+
+ /* Setup some critical 970 SPRs before switching MMU off */
+ mfspr r0,SPRN_PVR
+ srwi r0,r0,16
+ cmpwi r0,0x39 /* 970 */
+ beq 1f
+ cmpwi r0,0x3c /* 970FX */
+ beq 1f
+ cmpwi r0,0x44 /* 970MP */
+ beq 1f
+ cmpwi r0,0x45 /* 970GX */
+ bne 2f
+1: bl __cpu_preinit_ppc970
+2:
+
+ /* Switch off MMU if not already off */
+ bl __mmu_off
+
+ mtlr r25
+ blr
+#endif
/*
* Here is our main kernel entry point. We support currently 2 kind of entries
@@ -523,26 +545,10 @@ __start_initialization_multiplatform:
#ifdef CONFIG_PPC_BOOK3E_64
bl start_initialization_book3e
- b __after_prom_start
#else
- /* Setup some critical 970 SPRs before switching MMU off */
- mfspr r0,SPRN_PVR
- srwi r0,r0,16
- cmpwi r0,0x39 /* 970 */
- beq 1f
- cmpwi r0,0x3c /* 970FX */
- beq 1f
- cmpwi r0,0x44 /* 970MP */
- beq 1f
- cmpwi r0,0x45 /* 970GX */
- bne 2f
-1: bl __cpu_preinit_ppc970
-2:
-
- /* Switch off MMU if not already off */
- bl __mmu_off
- b __after_prom_start
+ bl start_initialization_book3s
#endif /* CONFIG_PPC_BOOK3E_64 */
+ b __after_prom_start
__REF
__boot_from_prom:
--
2.37.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/3] powerpc/64e: Simplify address calculation in secondary hold loop
2023-02-03 11:38 [PATCH 0/3] powerpc: prepare for pcrel addressing patches Nicholas Piggin
2023-02-03 11:38 ` [PATCH 1/3] crypto: powerpc - Use address generation helper for asm Nicholas Piggin
2023-02-03 11:38 ` [PATCH 2/3] powerpc/64s: Refactor initialisation after prom Nicholas Piggin
@ 2023-02-03 11:38 ` Nicholas Piggin
2023-02-15 12:40 ` [PATCH 0/3] powerpc: prepare for pcrel addressing patches Michael Ellerman
3 siblings, 0 replies; 5+ messages in thread
From: Nicholas Piggin @ 2023-02-03 11:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
As the earlier comment explains, __secondary_hold_spinloop does not have
to be accessed at its virtual address, slightly simplifying code.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/head_64.S | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 5af2e473b195..3a7266fa8a18 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -160,12 +160,8 @@ __secondary_hold:
std r24,(ABS_ADDR(__secondary_hold_acknowledge, first_256B))(0)
sync
- li r26,0
-#ifdef CONFIG_PPC_BOOK3E_64
- tovirt(r26,r26)
-#endif
/* All secondary cpus wait here until told to start. */
-100: ld r12,(ABS_ADDR(__secondary_hold_spinloop, first_256B))(r26)
+100: ld r12,(ABS_ADDR(__secondary_hold_spinloop, first_256B))(0)
cmpdi 0,r12,0
beq 100b
--
2.37.2
^ permalink raw reply related [flat|nested] 5+ messages in thread