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Wed, 22 Feb 2023 09:03:53 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7ACD82004B; Wed, 22 Feb 2023 09:03:53 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 67E0920043; Wed, 22 Feb 2023 09:03:50 +0000 (GMT) Received: from li-a450e7cc-27df-11b2-a85c-b5a9ac31e8ef.ibm.com (unknown [9.43.123.148]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 22 Feb 2023 09:03:50 +0000 (GMT) From: Kautuk Consul To: Michael Ellerman , Nicholas Piggin , Christophe Leroy , Rohan McLure Subject: [PATCH v2] arch/powerpc/include/asm/barrier.h: redefine rmb and wmb to lwsync Date: Wed, 22 Feb 2023 14:33:44 +0530 Message-Id: <20230222090344.189270-1-kconsul@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: NaYc2lZZu0jJ8X5W3gtlCbMrNFeQnFkQ X-Proofpoint-GUID: H6girN4eq9gcI0GUR15wgtr31GAK9Iij X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-22_04,2023-02-20_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 adultscore=0 mlxlogscore=837 mlxscore=0 malwarescore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302220078 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Kautuk Consul Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" A link from ibm.com states: "Ensures that all instructions preceding the call to __lwsync complete before any subsequent store instructions can be executed on the processor that executed the function. Also, it ensures that all load instructions preceding the call to __lwsync complete before any subsequent load instructions can be executed on the processor that executed the function. This allows you to synchronize between multiple processors with minimal performance impact, as __lwsync does not wait for confirmation from each processor." Thats why smp_rmb() and smp_wmb() are defined to lwsync. But this same understanding applies to parallel pipeline execution on each PowerPC processor. So, use the lwsync instruction for rmb() and wmb() on the PPC architectures that support it. Signed-off-by: Kautuk Consul --- arch/powerpc/include/asm/barrier.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/include/asm/barrier.h b/arch/powerpc/include/asm/barrier.h index b95b666f0374..e088dacc0ee8 100644 --- a/arch/powerpc/include/asm/barrier.h +++ b/arch/powerpc/include/asm/barrier.h @@ -36,8 +36,15 @@ * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio. */ #define __mb() __asm__ __volatile__ ("sync" : : : "memory") + +/* The sub-arch has lwsync. */ +#if defined(CONFIG_PPC64) || defined(CONFIG_PPC_E500MC) +#define __rmb() __asm__ __volatile__ ("lwsync" : : : "memory") +#define __wmb() __asm__ __volatile__ ("lwsync" : : : "memory") +#else #define __rmb() __asm__ __volatile__ ("sync" : : : "memory") #define __wmb() __asm__ __volatile__ ("sync" : : : "memory") +#endif /* The sub-arch has lwsync */ #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_E500MC) -- 2.31.1