From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A86AC6FA8E for ; Sun, 26 Feb 2023 17:49:16 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PPrjR26w5z3f8B for ; Mon, 27 Feb 2023 04:49:15 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=209.85.166.172; helo=mail-il1-f172.google.com; envelope-from=robherring2@gmail.com; receiver=) Received: from mail-il1-f172.google.com (mail-il1-f172.google.com [209.85.166.172]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PPrhs2jGtz30Ky for ; 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Sun, 26 Feb 2023 09:48:39 -0800 (PST) Received: from robh_at_kernel.org ([2605:ef80:8069:8ddf:ff6b:c94c:94fd:4442]) by smtp.gmail.com with ESMTPSA id z19-20020a056638001300b003a9595b7e3asm1479085jao.46.2023.02.26.09.48.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 09:48:38 -0800 (PST) Received: (nullmailer pid 84297 invoked by uid 1000); Sun, 26 Feb 2023 17:48:33 -0000 Date: Sun, 26 Feb 2023 11:48:33 -0600 From: Rob Herring To: Herve Codina Subject: Re: [PATCH v6 01/10] dt-bindings: soc: fsl: cpm_qe: Add TSA controller Message-ID: <20230226174833.GA76710-robh@kernel.org> References: <20230217145645.1768659-1-herve.codina@bootlin.com> <20230217145645.1768659-2-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230217145645.1768659-2-herve.codina@bootlin.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Fabio Estevam , linux-kernel@vger.kernel.org, Thomas Petazzoni , Xiubo Li , Takashi Iwai , Liam Girdwood , Li Yang , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, Mark Brown , Nicholas Piggin , Krzysztof Kozlowski , Jaroslav Kysela , Shengjiu Wang , linux-arm-kernel@lists.infradead.org, Qiang Zhao Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Fri, Feb 17, 2023 at 03:56:36PM +0100, Herve Codina wrote: > Add support for the time slot assigner (TSA) > available in some PowerQUICC SoC such as MPC885 > or MPC866. > > Signed-off-by: Herve Codina > --- > .../bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml | 215 ++++++++++++++++++ > include/dt-bindings/soc/cpm1-fsl,tsa.h | 13 ++ > 2 files changed, 228 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml > create mode 100644 include/dt-bindings/soc/cpm1-fsl,tsa.h > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml > new file mode 100644 > index 000000000000..332e902bcc21 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml > @@ -0,0 +1,215 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM Time-slot assigner (TSA) controller > + > +maintainers: > + - Herve Codina > + > +description: > + The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. > + Its purpose is to route some TDM time-slots to other internal serial > + controllers. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-tsa > + - fsl,mpc866-tsa > + - const: fsl,cpm1-tsa > + > + reg: > + items: > + - description: SI (Serial Interface) register base > + - description: SI RAM base > + > + reg-names: > + items: > + - const: si_regs > + - const: si_ram > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#fsl,serial-cells': #foo-cells is for when there are differing foo providers which need different number of cells. That's not the case here. > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 1 > + description: > + TSA consumers that use a phandle to TSA need to pass the serial identifier > + with this phandle (defined in dt-bindings/soc/fsl,tsa.h). > + For instance "fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;".