* [PATCH v2 01/12] powerpc/book3s: Add missing <linux/sched.h> include
2023-03-30 5:50 [PATCH v2 00/12] Add static DEXCR support Benjamin Gray
@ 2023-03-30 5:50 ` Benjamin Gray
2023-05-08 3:36 ` Russell Currey
2023-03-30 5:50 ` [PATCH v2 02/12] powerpc/ptrace: Add missing <linux/regset.h> include Benjamin Gray
` (10 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Benjamin Gray @ 2023-03-30 5:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: npiggin, Benjamin Gray
The functions here use struct thread_struct fields, so need to import
the full definition from <linux/sched.h>. The <asm/current.h> header
that defines current only forward declares struct thread_struct.
Failing to include this <linux/sched.h> header leads to a compilation
error when a translation unit does not also include <linux/sched.h>
indirectly.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
v1: * Add npiggin reviewed-by
---
arch/powerpc/include/asm/book3s/64/kup.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm/book3s/64/kup.h b/arch/powerpc/include/asm/book3s/64/kup.h
index 54cf46808157..84c09e546115 100644
--- a/arch/powerpc/include/asm/book3s/64/kup.h
+++ b/arch/powerpc/include/asm/book3s/64/kup.h
@@ -194,6 +194,7 @@
#else /* !__ASSEMBLY__ */
#include <linux/jump_label.h>
+#include <linux/sched.h>
DECLARE_STATIC_KEY_FALSE(uaccess_flush_key);
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 01/12] powerpc/book3s: Add missing <linux/sched.h> include
2023-03-30 5:50 ` [PATCH v2 01/12] powerpc/book3s: Add missing <linux/sched.h> include Benjamin Gray
@ 2023-05-08 3:36 ` Russell Currey
0 siblings, 0 replies; 23+ messages in thread
From: Russell Currey @ 2023-05-08 3:36 UTC (permalink / raw)
To: Benjamin Gray, linuxppc-dev; +Cc: npiggin
On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote:
> The functions here use struct thread_struct fields, so need to import
> the full definition from <linux/sched.h>. The <asm/current.h> header
> that defines current only forward declares struct thread_struct.
>
> Failing to include this <linux/sched.h> header leads to a compilation
> error when a translation unit does not also include <linux/sched.h>
> indirectly.
>
> Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
> Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Russell Currey <ruscur@russell.cc>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 02/12] powerpc/ptrace: Add missing <linux/regset.h> include
2023-03-30 5:50 [PATCH v2 00/12] Add static DEXCR support Benjamin Gray
2023-03-30 5:50 ` [PATCH v2 01/12] powerpc/book3s: Add missing <linux/sched.h> include Benjamin Gray
@ 2023-03-30 5:50 ` Benjamin Gray
2023-05-08 3:39 ` Russell Currey
2023-03-30 5:50 ` [PATCH v2 03/12] powerpc/dexcr: Add initial Dynamic Execution Control Register (DEXCR) support Benjamin Gray
` (9 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Benjamin Gray @ 2023-03-30 5:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: npiggin, Benjamin Gray
ptrace-decl.h uses user_regset_get2_fn (among other things) from
regset.h. While all current users of ptrace-decl.h include regset.h
before it anyway, it adds an implicit ordering dependency and breaks
source tooling that tries to inspect ptrace-decl.h by itself.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
---
v2: * New in v2
---
arch/powerpc/kernel/ptrace/ptrace-decl.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-decl.h b/arch/powerpc/kernel/ptrace/ptrace-decl.h
index eafe5f0f6289..463a63eb8cc7 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-decl.h
+++ b/arch/powerpc/kernel/ptrace/ptrace-decl.h
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <linux/regset.h>
+
/*
* Set of msr bits that gdb can change on behalf of a process.
*/
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 03/12] powerpc/dexcr: Add initial Dynamic Execution Control Register (DEXCR) support
2023-03-30 5:50 [PATCH v2 00/12] Add static DEXCR support Benjamin Gray
2023-03-30 5:50 ` [PATCH v2 01/12] powerpc/book3s: Add missing <linux/sched.h> include Benjamin Gray
2023-03-30 5:50 ` [PATCH v2 02/12] powerpc/ptrace: Add missing <linux/regset.h> include Benjamin Gray
@ 2023-03-30 5:50 ` Benjamin Gray
2023-05-08 3:44 ` Russell Currey
2023-03-30 5:50 ` [PATCH v2 04/12] powerpc/dexcr: Handle hashchk exception Benjamin Gray
` (8 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Benjamin Gray @ 2023-03-30 5:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: npiggin, Benjamin Gray
ISA 3.1B introduces the Dynamic Execution Control Register (DEXCR). It
is a per-cpu register that allows control over various CPU behaviours
including branch hint usage, indirect branch speculation, and
hashst/hashchk support.
Add some definitions and basic support for the DEXCR in the kernel.
Right now it just
* Zero initialises the DEXCR and HASHKEYR when a CPU onlines.
* Clears them in reset_sprs().
* Detects when the NPHIE aspect is supported (the others don't get
looked at in this series, so there's no need to waste a CPU_FTR
on them).
We initialise the HASHKEYR to ensure that all cores have the same key,
so an HV enforced NPHIE + swapping cores doesn't randomly crash a
process using hash instructions. The stores to HASHKEYR are
unconditional because the ISA makes no mention of the SPR being missing
if support for doing the hashes isn't present. So all that would happen
is the HASHKEYR value gets ignored. This helps slightly if NPHIE
detection fails; e.g., we currently only detect it on pseries.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
---
v2: * More definitions for ptrace
v1: * Only make a CPU feature for NPHIE. We only need to know if the
hashst/hashchk functionality is supported for a static DEXCR.
* Initialise the DEXCR to 0 when each CPU comes online. Remove
the dexcr_init() and get_thread_dexcr() functions.
* No longer track the DEXCR in a per-thread field.
* Remove the made-up Opal features
---
arch/powerpc/include/asm/book3s/64/kexec.h | 5 +++++
arch/powerpc/include/asm/cputable.h | 4 +++-
arch/powerpc/include/asm/reg.h | 10 ++++++++++
arch/powerpc/kernel/cpu_setup_power.c | 8 ++++++++
arch/powerpc/kernel/prom.c | 1 +
5 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/book3s/64/kexec.h b/arch/powerpc/include/asm/book3s/64/kexec.h
index d4b9d476ecba..df37a76c1e9f 100644
--- a/arch/powerpc/include/asm/book3s/64/kexec.h
+++ b/arch/powerpc/include/asm/book3s/64/kexec.h
@@ -21,6 +21,11 @@ static inline void reset_sprs(void)
plpar_set_ciabr(0);
}
+ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+ mtspr(SPRN_DEXCR, 0);
+ mtspr(SPRN_HASHKEYR, 0);
+ }
+
/* Do we need isync()? We are going via a kexec reset */
isync();
}
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 757dbded11dc..443a9d482b15 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -192,6 +192,7 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000)
#define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000)
#define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000)
+#define CPU_FTR_DEXCR_NPHIE LONG_ASM_CONST(0x0010000000000000)
#ifndef __ASSEMBLY__
@@ -451,7 +452,8 @@ static inline void cpu_feature_keys_init(void) { }
CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
- CPU_FTR_DAWR | CPU_FTR_DAWR1)
+ CPU_FTR_DAWR | CPU_FTR_DAWR1 | \
+ CPU_FTR_DEXCR_NPHIE)
#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1e8b2e04e626..70e043f1dce7 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -384,7 +384,17 @@
#define SPRN_HRMOR 0x139 /* Real mode offset register */
#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
+#define SPRN_HDEXCR_RO 0x1C7 /* Hypervisor DEXCR (non-privileged, readonly) */
+#define SPRN_HASHKEYR 0x1D4 /* Non-privileged hashst/hashchk key register */
+#define SPRN_HDEXCR 0x1D7 /* Hypervisor dynamic execution control register */
+#define SPRN_DEXCR_RO 0x32C /* DEXCR (non-privileged, readonly) */
#define SPRN_ASDR 0x330 /* Access segment descriptor register */
+#define SPRN_DEXCR 0x33C /* Dynamic execution control register */
+#define DEXCR_PR_BIT(aspect) PPC_BIT(32 + (aspect))
+#define DEXCR_PR_SBHE DEXCR_PR_BIT(0) /* Speculative Branch Hint Enable */
+#define DEXCR_PR_IBRTPD DEXCR_PR_BIT(3) /* Indirect Branch Recurrent Target Prediction Disable */
+#define DEXCR_PR_SRAPD DEXCR_PR_BIT(4) /* Subroutine Return Address Prediction Disable */
+#define DEXCR_PR_NPHIE DEXCR_PR_BIT(5) /* Non-Privileged Hash Instruction Enable */
#define SPRN_IC 0x350 /* Virtual Instruction Count */
#define SPRN_VTB 0x351 /* Virtual Time Base */
#define SPRN_LDBAR 0x352 /* LD Base Address Register */
diff --git a/arch/powerpc/kernel/cpu_setup_power.c b/arch/powerpc/kernel/cpu_setup_power.c
index 097c033668f0..c00721801a1b 100644
--- a/arch/powerpc/kernel/cpu_setup_power.c
+++ b/arch/powerpc/kernel/cpu_setup_power.c
@@ -126,6 +126,12 @@ static void init_PMU_ISA31(void)
mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMCCEXT);
}
+static void init_DEXCR(void)
+{
+ mtspr(SPRN_DEXCR, 0);
+ mtspr(SPRN_HASHKEYR, 0);
+}
+
/*
* Note that we can be called twice of pseudo-PVRs.
* The parameter offset is not used.
@@ -241,6 +247,7 @@ void __setup_cpu_power10(unsigned long offset, struct cpu_spec *t)
init_FSCR_power10();
init_PMU();
init_PMU_ISA31();
+ init_DEXCR();
if (!init_hvmode_206(t))
return;
@@ -263,6 +270,7 @@ void __restore_cpu_power10(void)
init_FSCR_power10();
init_PMU();
init_PMU_ISA31();
+ init_DEXCR();
msr = mfmsr();
if (!(msr & MSR_HV))
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 9d9ee4e9e1a1..0b5878c3125b 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -182,6 +182,7 @@ static struct ibm_feature ibm_pa_features[] __initdata = {
.cpu_user_ftrs2 = PPC_FEATURE2_HTM_COMP | PPC_FEATURE2_HTM_NOSC_COMP },
{ .pabyte = 64, .pabit = 0, .cpu_features = CPU_FTR_DAWR1 },
+ { .pabyte = 68, .pabit = 5, .cpu_features = CPU_FTR_DEXCR_NPHIE },
};
/*
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 03/12] powerpc/dexcr: Add initial Dynamic Execution Control Register (DEXCR) support
2023-03-30 5:50 ` [PATCH v2 03/12] powerpc/dexcr: Add initial Dynamic Execution Control Register (DEXCR) support Benjamin Gray
@ 2023-05-08 3:44 ` Russell Currey
0 siblings, 0 replies; 23+ messages in thread
From: Russell Currey @ 2023-05-08 3:44 UTC (permalink / raw)
To: Benjamin Gray, linuxppc-dev; +Cc: npiggin
On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote:
> ISA 3.1B introduces the Dynamic Execution Control Register (DEXCR).
> It
> is a per-cpu register that allows control over various CPU behaviours
> including branch hint usage, indirect branch speculation, and
> hashst/hashchk support.
>
> Add some definitions and basic support for the DEXCR in the kernel.
> Right now it just
>
> * Zero initialises the DEXCR and HASHKEYR when a CPU onlines.
> * Clears them in reset_sprs().
> * Detects when the NPHIE aspect is supported (the others don't get
> looked at in this series, so there's no need to waste a CPU_FTR
> on them).
>
> We initialise the HASHKEYR to ensure that all cores have the same
> key,
> so an HV enforced NPHIE + swapping cores doesn't randomly crash a
> process using hash instructions. The stores to HASHKEYR are
> unconditional because the ISA makes no mention of the SPR being
> missing
> if support for doing the hashes isn't present. So all that would
> happen
> is the HASHKEYR value gets ignored. This helps slightly if NPHIE
> detection fails; e.g., we currently only detect it on pseries.
>
> Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
>
LGTM.
Reviewed-by: Russell Currey <ruscur@russell.cc>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 04/12] powerpc/dexcr: Handle hashchk exception
2023-03-30 5:50 [PATCH v2 00/12] Add static DEXCR support Benjamin Gray
` (2 preceding siblings ...)
2023-03-30 5:50 ` [PATCH v2 03/12] powerpc/dexcr: Add initial Dynamic Execution Control Register (DEXCR) support Benjamin Gray
@ 2023-03-30 5:50 ` Benjamin Gray
2023-05-08 4:00 ` Russell Currey
2023-03-30 5:50 ` [PATCH v2 05/12] powerpc/dexcr: Support userspace ROP protection Benjamin Gray
` (7 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Benjamin Gray @ 2023-03-30 5:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: npiggin, Benjamin Gray
Recognise and pass the appropriate signal to the user program when a
hashchk instruction triggers. This is independent of allowing
configuration of DEXCR[NPHIE], as a hypervisor can enforce this aspect
regardless of the kernel.
The signal mirrors how ARM reports their similar check failure. For
example, their FPAC handler in arch/arm64/kernel/traps.c do_el0_fpac()
does this. When we fail to read the instruction that caused the fault
we send a segfault, similar to how emulate_math() does it.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
---
v1: * Refactor the hashchk check to return 0 on success, an error
code on failure. Determine what to do based on specific error
code.
* Motivate signal and code
---
arch/powerpc/include/asm/ppc-opcode.h | 1 +
arch/powerpc/include/asm/processor.h | 9 +++++++
arch/powerpc/kernel/Makefile | 1 +
arch/powerpc/kernel/dexcr.c | 36 +++++++++++++++++++++++++++
arch/powerpc/kernel/traps.c | 10 ++++++++
5 files changed, 57 insertions(+)
create mode 100644 arch/powerpc/kernel/dexcr.c
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 21e33e46f4b8..89b316466ed1 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -215,6 +215,7 @@
#define OP_31_XOP_STFSX 663
#define OP_31_XOP_STFSUX 695
#define OP_31_XOP_STFDX 727
+#define OP_31_XOP_HASHCHK 754
#define OP_31_XOP_STFDUX 759
#define OP_31_XOP_LHBRX 790
#define OP_31_XOP_LFIWAX 855
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index e96c9b8c2a60..bad64d6a5d36 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -455,6 +455,15 @@ int exit_vmx_usercopy(void);
int enter_vmx_ops(void);
void *exit_vmx_ops(void *dest);
+#ifdef CONFIG_PPC_BOOK3S_64
+int check_hashchk_trap(struct pt_regs const *regs);
+#else
+static inline int check_hashchk_trap(struct pt_regs const *regs)
+{
+ return -EINVAL;
+}
+#endif /* CONFIG_PPC_BOOK3S_64 */
+
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 9bf2be123093..07181e508754 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -88,6 +88,7 @@ obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
obj-$(CONFIG_PPC_DAWR) += dawr.o
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o
+obj-$(CONFIG_PPC_BOOK3S_64) += dexcr.o
obj-$(CONFIG_PPC_BOOK3S_64) += mce.o mce_power.o
obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_64e.o
obj-$(CONFIG_PPC_BARRIER_NOSPEC) += security.o
diff --git a/arch/powerpc/kernel/dexcr.c b/arch/powerpc/kernel/dexcr.c
new file mode 100644
index 000000000000..f263e5439cc6
--- /dev/null
+++ b/arch/powerpc/kernel/dexcr.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DEXCR infrastructure
+ *
+ * Copyright 2023, Benjamin Gray, IBM Corporation.
+ */
+#include <linux/compiler_types.h>
+
+#include <asm/cpu_has_feature.h>
+#include <asm/cputable.h>
+#include <asm/disassemble.h>
+#include <asm/errno.h>
+#include <asm/inst.h>
+#include <asm/ppc-opcode.h>
+#include <asm/ptrace.h>
+#include <asm/reg.h>
+
+int check_hashchk_trap(struct pt_regs const *regs)
+{
+ ppc_inst_t insn;
+
+ if (!cpu_has_feature(CPU_FTR_DEXCR_NPHIE))
+ return -EINVAL;
+
+ if (!user_mode(regs))
+ return -EINVAL;
+
+ if (get_user_instr(insn, (void __user *)regs->nip))
+ return -EFAULT;
+
+ if (ppc_inst_primary_opcode(insn) != 31 ||
+ get_xop(ppc_inst_val(insn)) != OP_31_XOP_HASHCHK)
+ return -EINVAL;
+
+ return 0;
+}
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 9bdd79aa51cf..ade67e23b974 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1516,6 +1516,16 @@ static void do_program_check(struct pt_regs *regs)
return;
}
}
+
+ switch (check_hashchk_trap(regs)) {
+ case 0:
+ _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
+ return;
+ case -EFAULT:
+ _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
+ return;
+ }
+
_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
return;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 04/12] powerpc/dexcr: Handle hashchk exception
2023-03-30 5:50 ` [PATCH v2 04/12] powerpc/dexcr: Handle hashchk exception Benjamin Gray
@ 2023-05-08 4:00 ` Russell Currey
0 siblings, 0 replies; 23+ messages in thread
From: Russell Currey @ 2023-05-08 4:00 UTC (permalink / raw)
To: Benjamin Gray, linuxppc-dev; +Cc: npiggin
On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote:
> Recognise and pass the appropriate signal to the user program when a
> hashchk instruction triggers. This is independent of allowing
> configuration of DEXCR[NPHIE], as a hypervisor can enforce this
> aspect
> regardless of the kernel.
>
> The signal mirrors how ARM reports their similar check failure. For
> example, their FPAC handler in arch/arm64/kernel/traps.c
> do_el0_fpac()
> does this. When we fail to read the instruction that caused the fault
> we send a segfault, similar to how emulate_math() does it.
>
> Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
>
> ---
>
> v1: * Refactor the hashchk check to return 0 on success, an error
> code on failure. Determine what to do based on specific
> error
> code.
0 on success makes sense, but it's not exactly obvious what "success"
is in this case.
> * Motivate signal and code
> ---
> arch/powerpc/include/asm/ppc-opcode.h | 1 +
> arch/powerpc/include/asm/processor.h | 9 +++++++
> arch/powerpc/kernel/Makefile | 1 +
> arch/powerpc/kernel/dexcr.c | 36
> +++++++++++++++++++++++++++
> arch/powerpc/kernel/traps.c | 10 ++++++++
> 5 files changed, 57 insertions(+)
> create mode 100644 arch/powerpc/kernel/dexcr.c
>
> diff --git a/arch/powerpc/include/asm/ppc-opcode.h
> b/arch/powerpc/include/asm/ppc-opcode.h
> index 21e33e46f4b8..89b316466ed1 100644
> --- a/arch/powerpc/include/asm/ppc-opcode.h
> +++ b/arch/powerpc/include/asm/ppc-opcode.h
> @@ -215,6 +215,7 @@
> #define OP_31_XOP_STFSX 663
> #define OP_31_XOP_STFSUX 695
> #define OP_31_XOP_STFDX 727
> +#define OP_31_XOP_HASHCHK 754
> #define OP_31_XOP_STFDUX 759
> #define OP_31_XOP_LHBRX 790
> #define OP_31_XOP_LFIWAX 855
> diff --git a/arch/powerpc/include/asm/processor.h
> b/arch/powerpc/include/asm/processor.h
> index e96c9b8c2a60..bad64d6a5d36 100644
> --- a/arch/powerpc/include/asm/processor.h
> +++ b/arch/powerpc/include/asm/processor.h
> @@ -455,6 +455,15 @@ int exit_vmx_usercopy(void);
> int enter_vmx_ops(void);
> void *exit_vmx_ops(void *dest);
>
> +#ifdef CONFIG_PPC_BOOK3S_64
> +int check_hashchk_trap(struct pt_regs const *regs);
> +#else
> +static inline int check_hashchk_trap(struct pt_regs const *regs)
> +{
> + return -EINVAL;
> +}
> +#endif /* CONFIG_PPC_BOOK3S_64 */
> +
> #endif /* __KERNEL__ */
> #endif /* __ASSEMBLY__ */
> #endif /* _ASM_POWERPC_PROCESSOR_H */
> diff --git a/arch/powerpc/kernel/Makefile
> b/arch/powerpc/kernel/Makefile
> index 9bf2be123093..07181e508754 100644
> --- a/arch/powerpc/kernel/Makefile
> +++ b/arch/powerpc/kernel/Makefile
> @@ -88,6 +88,7 @@ obj-$(CONFIG_HAVE_HW_BREAKPOINT) +=
> hw_breakpoint.o
> obj-$(CONFIG_PPC_DAWR) += dawr.o
> obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o
> cpu_setup_pa6t.o
> obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o
> +obj-$(CONFIG_PPC_BOOK3S_64) += dexcr.o
> obj-$(CONFIG_PPC_BOOK3S_64) += mce.o mce_power.o
> obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_64e.o
> obj-$(CONFIG_PPC_BARRIER_NOSPEC) += security.o
> diff --git a/arch/powerpc/kernel/dexcr.c
> b/arch/powerpc/kernel/dexcr.c
> new file mode 100644
> index 000000000000..f263e5439cc6
> --- /dev/null
> +++ b/arch/powerpc/kernel/dexcr.c
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * DEXCR infrastructure
May as well spell out DEXCR here
> + *
> + * Copyright 2023, Benjamin Gray, IBM Corporation.
> + */
> +#include <linux/compiler_types.h>
> +
> +#include <asm/cpu_has_feature.h>
> +#include <asm/cputable.h>
> +#include <asm/disassemble.h>
> +#include <asm/errno.h>
> +#include <asm/inst.h>
> +#include <asm/ppc-opcode.h>
> +#include <asm/ptrace.h>
> +#include <asm/reg.h>
> +
> +int check_hashchk_trap(struct pt_regs const *regs)
> +{
> + ppc_inst_t insn;
> +
> + if (!cpu_has_feature(CPU_FTR_DEXCR_NPHIE))
> + return -EINVAL;
> +
> + if (!user_mode(regs))
> + return -EINVAL;
> +
> + if (get_user_instr(insn, (void __user *)regs->nip))
> + return -EFAULT;
> +
> + if (ppc_inst_primary_opcode(insn) != 31 ||
> + get_xop(ppc_inst_val(insn)) != OP_31_XOP_HASHCHK)
> + return -EINVAL;
> +
> + return 0;
> +}
The return values here are quite confusing and only start to make sense
in the context of the calling function, which isn't great for something
living in a different file. So if we return 0 we SIGILL because of
hashchk, return -EFAULT to SEGV_MAPERR and return -EINVAL to fall
through to SIGTRAP. I would like a comment for that since it's not
very intuitive.
> diff --git a/arch/powerpc/kernel/traps.c
> b/arch/powerpc/kernel/traps.c
> index 9bdd79aa51cf..ade67e23b974 100644
> --- a/arch/powerpc/kernel/traps.c
> +++ b/arch/powerpc/kernel/traps.c
> @@ -1516,6 +1516,16 @@ static void do_program_check(struct pt_regs
> *regs)
> return;
> }
> }
> +
> + switch (check_hashchk_trap(regs)) {
> + case 0:
> + _exception(SIGILL, regs, ILL_ILLOPN, regs-
> >nip);
> + return;
> + case -EFAULT:
> + _exception(SIGSEGV, regs, SEGV_MAPERR, regs-
> >nip);
> + return;
> + }
> +
I offer no constructive feedback on how to rearrange it, but this just
looks gross.
> _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
> return;
> }
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 05/12] powerpc/dexcr: Support userspace ROP protection
2023-03-30 5:50 [PATCH v2 00/12] Add static DEXCR support Benjamin Gray
` (3 preceding siblings ...)
2023-03-30 5:50 ` [PATCH v2 04/12] powerpc/dexcr: Handle hashchk exception Benjamin Gray
@ 2023-03-30 5:50 ` Benjamin Gray
2023-05-08 4:10 ` Russell Currey
2023-03-30 5:50 ` [PATCH v2 06/12] powerpc/dexcr: Support custom default DEXCR value Benjamin Gray
` (6 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Benjamin Gray @ 2023-03-30 5:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: npiggin, Benjamin Gray
The ISA 3.1B hashst and hashchk instructions use a per-cpu SPR HASHKEYR
to hold a key used in the hash calculation. This key should be different
for each process to make it harder for a malicious process to recreate
valid hash values for a victim process.
Add support for storing a per-thread hash key, and setting/clearing
HASHKEYR appropriately.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
---
v1: * Guard HASHKEYR update behind change check
* HASHKEYR reset moved earlier to patch 2
---
arch/powerpc/include/asm/processor.h | 1 +
arch/powerpc/kernel/process.c | 17 +++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index bad64d6a5d36..666d4e9804a8 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -264,6 +264,7 @@ struct thread_struct {
unsigned long mmcr3;
unsigned long sier2;
unsigned long sier3;
+ unsigned long hashkeyr;
#endif
};
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index a7f9f3f85e20..a966adb5447f 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1182,6 +1182,9 @@ static inline void save_sprs(struct thread_struct *t)
*/
t->tar = mfspr(SPRN_TAR);
}
+
+ if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE))
+ t->hashkeyr = mfspr(SPRN_HASHKEYR);
#endif
}
@@ -1260,6 +1263,10 @@ static inline void restore_sprs(struct thread_struct *old_thread,
if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
old_thread->tidr != new_thread->tidr)
mtspr(SPRN_TIDR, new_thread->tidr);
+
+ if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE) &&
+ old_thread->hashkeyr != new_thread->hashkeyr)
+ mtspr(SPRN_HASHKEYR, new_thread->hashkeyr);
#endif
}
@@ -1844,6 +1851,10 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
childregs->ppr = DEFAULT_PPR;
p->thread.tidr = 0;
+#endif
+#ifdef CONFIG_PPC_BOOK3S_64
+ if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE))
+ p->thread.hashkeyr = current->thread.hashkeyr;
#endif
/*
* Run with the current AMR value of the kernel
@@ -1972,6 +1983,12 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
current->thread.tm_tfiar = 0;
current->thread.load_tm = 0;
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
+#ifdef CONFIG_PPC_BOOK3S_64
+ if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE)) {
+ current->thread.hashkeyr = get_random_long();
+ mtspr(SPRN_HASHKEYR, current->thread.hashkeyr);
+ }
+#endif /* CONFIG_PPC_BOOK3S_64 */
}
EXPORT_SYMBOL(start_thread);
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 05/12] powerpc/dexcr: Support userspace ROP protection
2023-03-30 5:50 ` [PATCH v2 05/12] powerpc/dexcr: Support userspace ROP protection Benjamin Gray
@ 2023-05-08 4:10 ` Russell Currey
0 siblings, 0 replies; 23+ messages in thread
From: Russell Currey @ 2023-05-08 4:10 UTC (permalink / raw)
To: Benjamin Gray, linuxppc-dev; +Cc: npiggin
On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote:
> The ISA 3.1B hashst and hashchk instructions use a per-cpu SPR
> HASHKEYR
> to hold a key used in the hash calculation. This key should be
> different
> for each process to make it harder for a malicious process to
> recreate
> valid hash values for a victim process.
>
> Add support for storing a per-thread hash key, and setting/clearing
> HASHKEYR appropriately.
>
> Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
Reviewed-by: Russell Currey <ruscur@russell.cc>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 06/12] powerpc/dexcr: Support custom default DEXCR value
2023-03-30 5:50 [PATCH v2 00/12] Add static DEXCR support Benjamin Gray
` (4 preceding siblings ...)
2023-03-30 5:50 ` [PATCH v2 05/12] powerpc/dexcr: Support userspace ROP protection Benjamin Gray
@ 2023-03-30 5:50 ` Benjamin Gray
2023-05-08 4:24 ` Russell Currey
2023-03-30 5:50 ` [PATCH v2 07/12] powerpc/ptrace: Expose DEXCR and HDEXCR registers to ptrace Benjamin Gray
` (5 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Benjamin Gray @ 2023-03-30 5:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: npiggin, Benjamin Gray
Make the DEXCR value configurable at config time. Intentionally don't
limit possible values to support future aspects without needing kernel
updates.
The default config value enables hashst/hashchk in problem state.
This should be safe, as generally software needs to request these
instructions be included in the first place.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
---
New in v1
Preface with: I'm note sure on the best place to put the config.
I also don't think there's any need to zero out unknown/unsupported
bits. Reserved implies they are ignored by the hardware (from my
understanding of the ISA). Current P10s boot with all bits set; lsdexcr
(later patch) reports
uDEXCR: ff000000 (SBHE, IBRTPD, SRAPD, NPHIE, PHIE, unknown)
when you try to read it back. Leaving them be also makes it easier to
support newer aspects without a kernel update.
If arbitrary value support isn't important, it's probably a nicer
interface to make each aspect an entry in a menu.
Future work may include dynamic DEXCR controls via prctl() and sysfs.
The dynamic controls would be able to override this default DEXCR on a
per-process basis. A stronger "PPC_ENFORCE_USER_ROP_PROCTETION" config
may be required at such a time to prevent dynamically disabling the
hash checks.
---
arch/powerpc/Kconfig | 14 ++++++++++++++
arch/powerpc/kernel/cpu_setup_power.c | 3 ++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 47017975fc2b..809ae576e19f 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -1035,6 +1035,20 @@ config PPC_MEM_KEYS
If unsure, say y.
+config PPC_DEXCR_DEFAULT
+ hex "Default DEXCR value"
+ default 0x0000000004000000
+ depends on PPC_BOOK3S_64
+ help
+ Power10 introduces the Dynamic Execution Control Register (DEXCR)
+ to provide fine grained control over various speculation and
+ security capabilities. This is used as the default DEXCR value.
+
+ It is a 64 bit value that splits into 32 bits for supervisor mode
+ and 32 bits for problem state. The default config value enables
+ the hashst/hashck instructions in userspace. See the ISA for
+ specifics of what each bit controls.
+
config PPC_SECURE_BOOT
prompt "Enable secure boot support"
bool
diff --git a/arch/powerpc/kernel/cpu_setup_power.c b/arch/powerpc/kernel/cpu_setup_power.c
index c00721801a1b..814c825a0661 100644
--- a/arch/powerpc/kernel/cpu_setup_power.c
+++ b/arch/powerpc/kernel/cpu_setup_power.c
@@ -10,6 +10,7 @@
#include <asm/reg.h>
#include <asm/synch.h>
#include <linux/bitops.h>
+#include <linux/kconfig.h>
#include <asm/cputable.h>
#include <asm/cpu_setup.h>
@@ -128,7 +129,7 @@ static void init_PMU_ISA31(void)
static void init_DEXCR(void)
{
- mtspr(SPRN_DEXCR, 0);
+ mtspr(SPRN_DEXCR, CONFIG_PPC_DEXCR_DEFAULT);
mtspr(SPRN_HASHKEYR, 0);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 06/12] powerpc/dexcr: Support custom default DEXCR value
2023-03-30 5:50 ` [PATCH v2 06/12] powerpc/dexcr: Support custom default DEXCR value Benjamin Gray
@ 2023-05-08 4:24 ` Russell Currey
0 siblings, 0 replies; 23+ messages in thread
From: Russell Currey @ 2023-05-08 4:24 UTC (permalink / raw)
To: Benjamin Gray, linuxppc-dev; +Cc: npiggin
On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote:
> Make the DEXCR value configurable at config time. Intentionally don't
> limit possible values to support future aspects without needing
> kernel
> updates.
>
> The default config value enables hashst/hashchk in problem state.
> This should be safe, as generally software needs to request these
> instructions be included in the first place.
>
> Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
>
Reviewed-by: Russell Currey <ruscur@russell.cc>
> ---
> New in v1
>
> Preface with: I'm note sure on the best place to put the config.
Me neither.
>
> I also don't think there's any need to zero out unknown/unsupported
> bits. Reserved implies they are ignored by the hardware (from my
> understanding of the ISA). Current P10s boot with all bits set;
> lsdexcr
> (later patch) reports
>
> uDEXCR: ff000000 (SBHE, IBRTPD, SRAPD, NPHIE, PHIE, unknown)
>
> when you try to read it back. Leaving them be also makes it easier to
> support newer aspects without a kernel update.
>
> If arbitrary value support isn't important, it's probably a nicer
> interface to make each aspect an entry in a menu.
>
> Future work may include dynamic DEXCR controls via prctl() and sysfs.
> The dynamic controls would be able to override this default DEXCR on
> a
> per-process basis. A stronger "PPC_ENFORCE_USER_ROP_PROCTETION"
> config
> may be required at such a time to prevent dynamically disabling the
> hash checks.
> ---
> arch/powerpc/Kconfig | 14 ++++++++++++++
> arch/powerpc/kernel/cpu_setup_power.c | 3 ++-
> 2 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 47017975fc2b..809ae576e19f 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -1035,6 +1035,20 @@ config PPC_MEM_KEYS
>
> If unsure, say y.
>
> +config PPC_DEXCR_DEFAULT
Calling it "default" could be slightly misleading since there's no
other way to modify the DEXCR right now. It'll make more sense once
it's user configurable though.
> + hex "Default DEXCR value"
> + default 0x0000000004000000
> + depends on PPC_BOOK3S_64
> + help
> + Power10 introduces the Dynamic Execution Control Register
> (DEXCR)
> + to provide fine grained control over various speculation
> and
> + security capabilities. This is used as the default DEXCR
> value.
> +
> + It is a 64 bit value that splits into 32 bits for
> supervisor mode
> + and 32 bits for problem state. The default config value
> enables
> + the hashst/hashck instructions in userspace. See the ISA
> for
hashchk*
May also be useful to reference the ISA version here.
> + specifics of what each bit controls.
> +
> config PPC_SECURE_BOOT
> prompt "Enable secure boot support"
> bool
> diff --git a/arch/powerpc/kernel/cpu_setup_power.c
> b/arch/powerpc/kernel/cpu_setup_power.c
> index c00721801a1b..814c825a0661 100644
> --- a/arch/powerpc/kernel/cpu_setup_power.c
> +++ b/arch/powerpc/kernel/cpu_setup_power.c
> @@ -10,6 +10,7 @@
> #include <asm/reg.h>
> #include <asm/synch.h>
> #include <linux/bitops.h>
> +#include <linux/kconfig.h>
> #include <asm/cputable.h>
> #include <asm/cpu_setup.h>
>
> @@ -128,7 +129,7 @@ static void init_PMU_ISA31(void)
>
> static void init_DEXCR(void)
> {
> - mtspr(SPRN_DEXCR, 0);
> + mtspr(SPRN_DEXCR, CONFIG_PPC_DEXCR_DEFAULT);
> mtspr(SPRN_HASHKEYR, 0);
> }
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 07/12] powerpc/ptrace: Expose DEXCR and HDEXCR registers to ptrace
2023-03-30 5:50 [PATCH v2 00/12] Add static DEXCR support Benjamin Gray
` (5 preceding siblings ...)
2023-03-30 5:50 ` [PATCH v2 06/12] powerpc/dexcr: Support custom default DEXCR value Benjamin Gray
@ 2023-03-30 5:50 ` Benjamin Gray
2023-05-08 4:30 ` Russell Currey
2023-03-30 5:50 ` [PATCH v2 08/12] powerpc/ptrace: Expose HASHKEYR register " Benjamin Gray
` (4 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Benjamin Gray @ 2023-03-30 5:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: npiggin, Benjamin Gray
The DEXCR register is of interest when ptracing processes. Currently it
is static, but eventually will be dynamically controllable by a process.
If a process can control its own, then it is useful for it to be
ptrace-able to (e.g., for checkpoint-restore functionality).
It is also relevant to core dumps (the NPHIE aspect in particular),
which use the ptrace mechanism (or is it the other way around?) to
decide what to dump. The HDEXCR is useful here too, as the NPHIE aspect
may be set in the HDEXCR without being set in the DEXCR. Although the
HDEXCR is per-cpu and we don't track it in the task struct (it's useless
in normal operation), it would be difficult to imagine why a hypervisor
would set it to different values within a guest. A hypervisor cannot
safely set NPHIE differently at least, as that would break programs.
Expose a read-only view of the userspace DEXCR and HDEXCR to ptrace.
The HDEXCR is always readonly, and is useful for diagnosing the core
dumps (as the HDEXCR may set NPHIE without the DEXCR setting it).
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
---
v2: * New in v2
---
arch/powerpc/include/uapi/asm/elf.h | 1 +
arch/powerpc/kernel/ptrace/ptrace-decl.h | 1 +
arch/powerpc/kernel/ptrace/ptrace-view.c | 31 +++++++++++++++++++++++-
include/uapi/linux/elf.h | 1 +
4 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/uapi/asm/elf.h b/arch/powerpc/include/uapi/asm/elf.h
index 308857123a08..de13ed7f0972 100644
--- a/arch/powerpc/include/uapi/asm/elf.h
+++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -98,6 +98,7 @@
#define ELF_NEBB 3 /* includes ebbrr, ebbhr, bescr */
#define ELF_NPMU 5 /* includes siar, sdar, sier, mmcr2, mmcr0 */
#define ELF_NPKEY 3 /* includes amr, iamr, uamor */
+#define ELF_NDEXCR 2 /* includes dexcr, hdexcr */
typedef unsigned long elf_greg_t64;
typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
diff --git a/arch/powerpc/kernel/ptrace/ptrace-decl.h b/arch/powerpc/kernel/ptrace/ptrace-decl.h
index 463a63eb8cc7..998a84f64804 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-decl.h
+++ b/arch/powerpc/kernel/ptrace/ptrace-decl.h
@@ -57,6 +57,7 @@ enum powerpc_regset {
REGSET_TAR, /* TAR register */
REGSET_EBB, /* EBB registers */
REGSET_PMR, /* Performance Monitor Registers */
+ REGSET_DEXCR, /* DEXCR registers */
#endif
#ifdef CONFIG_PPC_MEM_KEYS
REGSET_PKEY, /* AMR register */
diff --git a/arch/powerpc/kernel/ptrace/ptrace-view.c b/arch/powerpc/kernel/ptrace/ptrace-view.c
index 5fff0d04b23f..d3304fb932fa 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-view.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-view.c
@@ -454,7 +454,31 @@ static int pmu_set(struct task_struct *target, const struct user_regset *regset,
5 * sizeof(unsigned long));
return ret;
}
-#endif
+
+static int dexcr_active(struct task_struct *target, const struct user_regset *regset)
+{
+ if (!cpu_has_feature(CPU_FTR_ARCH_31))
+ return -ENODEV;
+
+ return regset->n;
+}
+
+static int dexcr_get(struct task_struct *target, const struct user_regset *regset,
+ struct membuf to)
+{
+ if (!cpu_has_feature(CPU_FTR_ARCH_31))
+ return -ENODEV;
+
+ membuf_store(&to, (unsigned int)CONFIG_PPC_DEXCR_DEFAULT);
+
+ /*
+ * Technically the HDEXCR is per-cpu, but a hypervisor can't reasonably
+ * change it between CPUs of the same guest.
+ */
+ return membuf_store(&to, (unsigned int)mfspr(SPRN_HDEXCR_RO));
+}
+
+#endif /* CONFIG_PPC_BOOK3S_64 */
#ifdef CONFIG_PPC_MEM_KEYS
static int pkey_active(struct task_struct *target, const struct user_regset *regset)
@@ -615,6 +639,11 @@ static const struct user_regset native_regsets[] = {
.size = sizeof(u64), .align = sizeof(u64),
.active = pmu_active, .regset_get = pmu_get, .set = pmu_set
},
+ [REGSET_DEXCR] = {
+ .core_note_type = NT_PPC_DEXCR, .n = ELF_NDEXCR,
+ .size = sizeof(u32), .align = sizeof(u32),
+ .active = dexcr_active, .regset_get = dexcr_get
+ },
#endif
#ifdef CONFIG_PPC_MEM_KEYS
[REGSET_PKEY] = {
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index ac3da855fb19..cfa31f1eb5d7 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -403,6 +403,7 @@ typedef struct elf64_shdr {
#define NT_PPC_TM_CPPR 0x10e /* TM checkpointed Program Priority Register */
#define NT_PPC_TM_CDSCR 0x10f /* TM checkpointed Data Stream Control Register */
#define NT_PPC_PKEY 0x110 /* Memory Protection Keys registers */
+#define NT_PPC_DEXCR 0x111 /* PowerPC DEXCR registers */
#define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */
#define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */
#define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 07/12] powerpc/ptrace: Expose DEXCR and HDEXCR registers to ptrace
2023-03-30 5:50 ` [PATCH v2 07/12] powerpc/ptrace: Expose DEXCR and HDEXCR registers to ptrace Benjamin Gray
@ 2023-05-08 4:30 ` Russell Currey
0 siblings, 0 replies; 23+ messages in thread
From: Russell Currey @ 2023-05-08 4:30 UTC (permalink / raw)
To: Benjamin Gray, linuxppc-dev; +Cc: npiggin
On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote:
> The DEXCR register is of interest when ptracing processes. Currently
> it
> is static, but eventually will be dynamically controllable by a
> process.
> If a process can control its own, then it is useful for it to be
> ptrace-able to (e.g., for checkpoint-restore functionality).
>
> It is also relevant to core dumps (the NPHIE aspect in particular),
> which use the ptrace mechanism (or is it the other way around?) to
> decide what to dump. The HDEXCR is useful here too, as the NPHIE
> aspect
> may be set in the HDEXCR without being set in the DEXCR. Although the
> HDEXCR is per-cpu and we don't track it in the task struct (it's
> useless
> in normal operation), it would be difficult to imagine why a
> hypervisor
> would set it to different values within a guest. A hypervisor cannot
> safely set NPHIE differently at least, as that would break programs.
>
> Expose a read-only view of the userspace DEXCR and HDEXCR to ptrace.
> The HDEXCR is always readonly, and is useful for diagnosing the core
> dumps (as the HDEXCR may set NPHIE without the DEXCR setting it).
>
> Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
>
I don't know much about ptrace but this looks sane.
Reviewed-by: Russell Currey <ruscur@russell.cc>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 08/12] powerpc/ptrace: Expose HASHKEYR register to ptrace
2023-03-30 5:50 [PATCH v2 00/12] Add static DEXCR support Benjamin Gray
` (6 preceding siblings ...)
2023-03-30 5:50 ` [PATCH v2 07/12] powerpc/ptrace: Expose DEXCR and HDEXCR registers to ptrace Benjamin Gray
@ 2023-03-30 5:50 ` Benjamin Gray
2023-05-08 4:32 ` Russell Currey
2023-03-30 5:50 ` [PATCH v2 09/12] Documentation: Document PowerPC kernel DEXCR interface Benjamin Gray
` (3 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Benjamin Gray @ 2023-03-30 5:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: npiggin, Benjamin Gray
The HASHKEYR register contains a secret per-process key to enable unique
hashes per process. In general it should not be exposed to userspace
at all and a regular process has no need to know its key.
However, checkpoint restore in userspace (CRIU) functionality requires
that a process be able to set the HASHKEYR of another process, otherwise
existing hashes on the stack would be invalidated by a new random key.
Exposing HASHKEYR in this way also makes it appear in core dumps, which
is a security concern. Multiple threads may share a key, for example
just after a fork() call, where the kernel cannot know if the child is
going to return back along the parent's stack. If such a thread is
coerced into making a core dump, then the HASHKEYR value will be
readable and able to be used against all other threads sharing that key,
effectively undoing any protection offered by hashst/hashchk.
Therefore we expose HASHKEYR to ptrace when CONFIG_CHECKPOINT_RESTORE is
enabled, providing a choice of increased security or migratable ROP
protected processes. This is similar to how ARM exposes its PAC keys.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
---
v2: * New in v2
---
arch/powerpc/include/uapi/asm/elf.h | 1 +
arch/powerpc/kernel/ptrace/ptrace-decl.h | 3 ++
arch/powerpc/kernel/ptrace/ptrace-view.c | 36 ++++++++++++++++++++++++
include/uapi/linux/elf.h | 1 +
4 files changed, 41 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/elf.h b/arch/powerpc/include/uapi/asm/elf.h
index de13ed7f0972..d7b1778738ea 100644
--- a/arch/powerpc/include/uapi/asm/elf.h
+++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -99,6 +99,7 @@
#define ELF_NPMU 5 /* includes siar, sdar, sier, mmcr2, mmcr0 */
#define ELF_NPKEY 3 /* includes amr, iamr, uamor */
#define ELF_NDEXCR 2 /* includes dexcr, hdexcr */
+#define ELF_NHASHKEYR 1 /* includes hashkeyr */
typedef unsigned long elf_greg_t64;
typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
diff --git a/arch/powerpc/kernel/ptrace/ptrace-decl.h b/arch/powerpc/kernel/ptrace/ptrace-decl.h
index 998a84f64804..4171a5727197 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-decl.h
+++ b/arch/powerpc/kernel/ptrace/ptrace-decl.h
@@ -58,6 +58,9 @@ enum powerpc_regset {
REGSET_EBB, /* EBB registers */
REGSET_PMR, /* Performance Monitor Registers */
REGSET_DEXCR, /* DEXCR registers */
+#ifdef CONFIG_CHECKPOINT_RESTORE
+ REGSET_HASHKEYR, /* HASHKEYR register */
+#endif
#endif
#ifdef CONFIG_PPC_MEM_KEYS
REGSET_PKEY, /* AMR register */
diff --git a/arch/powerpc/kernel/ptrace/ptrace-view.c b/arch/powerpc/kernel/ptrace/ptrace-view.c
index d3304fb932fa..acbb8ec11b1e 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-view.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-view.c
@@ -478,6 +478,35 @@ static int dexcr_get(struct task_struct *target, const struct user_regset *regse
return membuf_store(&to, (unsigned int)mfspr(SPRN_HDEXCR_RO));
}
+#ifdef CONFIG_CHECKPOINT_RESTORE
+static int hashkeyr_active(struct task_struct *target, const struct user_regset *regset)
+{
+ if (!cpu_has_feature(CPU_FTR_ARCH_31))
+ return -ENODEV;
+
+ return regset->n;
+}
+
+static int hashkeyr_get(struct task_struct *target, const struct user_regset *regset,
+ struct membuf to)
+{
+ if (!cpu_has_feature(CPU_FTR_ARCH_31))
+ return -ENODEV;
+
+ return membuf_store(&to, target->thread.hashkeyr);
+}
+
+static int hashkeyr_set(struct task_struct *target, const struct user_regset *regset,
+ unsigned int pos, unsigned int count, const void *kbuf,
+ const void __user *ubuf)
+{
+ if (!cpu_has_feature(CPU_FTR_ARCH_31))
+ return -ENODEV;
+
+ return user_regset_copyin(&pos, &count, &kbuf, &ubuf, &target->thread.hashkeyr,
+ 0, sizeof(unsigned long));
+}
+#endif /* CONFIG_CHECKPOINT_RESTORE */
#endif /* CONFIG_PPC_BOOK3S_64 */
#ifdef CONFIG_PPC_MEM_KEYS
@@ -644,6 +673,13 @@ static const struct user_regset native_regsets[] = {
.size = sizeof(u32), .align = sizeof(u32),
.active = dexcr_active, .regset_get = dexcr_get
},
+#ifdef CONFIG_CHECKPOINT_RESTORE
+ [REGSET_HASHKEYR] = {
+ .core_note_type = NT_PPC_HASHKEYR, .n = ELF_NHASHKEYR,
+ .size = sizeof(u64), .align = sizeof(u64),
+ .active = hashkeyr_active, .regset_get = hashkeyr_get, .set = hashkeyr_set
+ },
+#endif
#endif
#ifdef CONFIG_PPC_MEM_KEYS
[REGSET_PKEY] = {
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index cfa31f1eb5d7..b705b301d88f 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -404,6 +404,7 @@ typedef struct elf64_shdr {
#define NT_PPC_TM_CDSCR 0x10f /* TM checkpointed Data Stream Control Register */
#define NT_PPC_PKEY 0x110 /* Memory Protection Keys registers */
#define NT_PPC_DEXCR 0x111 /* PowerPC DEXCR registers */
+#define NT_PPC_HASHKEYR 0x112 /* PowerPC HASHKEYR register */
#define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */
#define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */
#define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 08/12] powerpc/ptrace: Expose HASHKEYR register to ptrace
2023-03-30 5:50 ` [PATCH v2 08/12] powerpc/ptrace: Expose HASHKEYR register " Benjamin Gray
@ 2023-05-08 4:32 ` Russell Currey
0 siblings, 0 replies; 23+ messages in thread
From: Russell Currey @ 2023-05-08 4:32 UTC (permalink / raw)
To: Benjamin Gray, linuxppc-dev; +Cc: npiggin
On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote:
> The HASHKEYR register contains a secret per-process key to enable
> unique
> hashes per process. In general it should not be exposed to userspace
> at all and a regular process has no need to know its key.
>
> However, checkpoint restore in userspace (CRIU) functionality
> requires
> that a process be able to set the HASHKEYR of another process,
> otherwise
> existing hashes on the stack would be invalidated by a new random
> key.
>
> Exposing HASHKEYR in this way also makes it appear in core dumps,
> which
> is a security concern. Multiple threads may share a key, for example
> just after a fork() call, where the kernel cannot know if the child
> is
> going to return back along the parent's stack. If such a thread is
> coerced into making a core dump, then the HASHKEYR value will be
> readable and able to be used against all other threads sharing that
> key,
> effectively undoing any protection offered by hashst/hashchk.
>
> Therefore we expose HASHKEYR to ptrace when CONFIG_CHECKPOINT_RESTORE
> is
> enabled, providing a choice of increased security or migratable ROP
> protected processes. This is similar to how ARM exposes its PAC keys.
>
> Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
Seems sensible
Reviewed-by: Russell Currey <ruscur@russell.cc>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 09/12] Documentation: Document PowerPC kernel DEXCR interface
2023-03-30 5:50 [PATCH v2 00/12] Add static DEXCR support Benjamin Gray
` (7 preceding siblings ...)
2023-03-30 5:50 ` [PATCH v2 08/12] powerpc/ptrace: Expose HASHKEYR register " Benjamin Gray
@ 2023-03-30 5:50 ` Benjamin Gray
2023-05-08 4:40 ` Russell Currey
2023-03-30 5:50 ` [PATCH v2 10/12] selftests/powerpc: Add more utility macros Benjamin Gray
` (2 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Benjamin Gray @ 2023-03-30 5:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: npiggin, Benjamin Gray
Describe the DEXCR and document how to configure it.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
---
v2: * Document coredump & ptrace support
v1: * Remove the dynamic control docs, describe the static config
option
This documentation is a little bare for now, but will be expanded on
when dynamic DEXCR control is added.
---
Documentation/powerpc/dexcr.rst | 58 +++++++++++++++++++++++++++++++++
Documentation/powerpc/index.rst | 1 +
2 files changed, 59 insertions(+)
create mode 100644 Documentation/powerpc/dexcr.rst
diff --git a/Documentation/powerpc/dexcr.rst b/Documentation/powerpc/dexcr.rst
new file mode 100644
index 000000000000..75f1efaa8dc5
--- /dev/null
+++ b/Documentation/powerpc/dexcr.rst
@@ -0,0 +1,58 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+==========================================
+DEXCR (Dynamic Execution Control Register)
+==========================================
+
+Overview
+========
+
+The DEXCR is a privileged special purpose register (SPR) introduced in
+PowerPC ISA 3.1B (Power10) that allows per-cpu control over several dynamic
+execution behaviours. These behaviours include speculation (e.g., indirect
+branch target prediction) and enabling return-oriented programming (ROP)
+protection instructions.
+
+The execution control is exposed in hardware as up to 32 bits ('aspects') in
+the DEXCR. Each aspect controls a certain behaviour, and can be set or cleared
+to enable/disable the aspect. There are several variants of the DEXCR for
+different purposes:
+
+DEXCR
+ A privileged SPR that can control aspects for userspace and kernel space
+HDEXCR
+ A hypervisor-privileged SPR that can control aspects for the hypervisor and
+ enforce aspects for the kernel and userspace.
+UDEXCR
+ An optional ultravisor-privileged SPR that can control aspects for the ultravisor.
+
+Userspace can examine the current DEXCR state using a dedicated SPR that
+provides a non-privileged read-only view of the userspace DEXCR aspects.
+There is also an SPR that provides a read-only view of the hypervisor enforced
+aspects, which ORed with the userspace DEXCR view gives the effective DEXCR
+state for a process.
+
+
+Kernel Config
+=============
+
+The kernel supports a static default DEXCR value determined at config time.
+Set the ``PPC_DEXCR_DEFAULT`` config to the value you want all processes to
+use.
+
+
+coredump and ptrace
+===================
+
+The userspace values of the DEXCR and HDEXCR (in this order) are exposed under
+``NT_PPC_DEXCR``. These are each 32 bits and readonly, and are intended to
+assist with core dumps. The DEXCR may be made writable in future.
+
+If the kernel config ``CONFIG_CHECKPOINT_RESTORE`` is enabled, then
+``NT_PPC_HASHKEYR`` is available and exposes the HASHKEYR value of the process
+for reading and writing. This is a tradeoff between increased security and
+checkpoint/restore support: a process should normally have no need to know its
+secret key, but restoring a process requires setting its original key. The key
+therefore appears in core dumps, and an attacker may be able to retrieve it from
+a coredump and effectively bypass ROP protection on any threads that share this
+key (potentially all threads from the same parent that have not run ``exec()``).
diff --git a/Documentation/powerpc/index.rst b/Documentation/powerpc/index.rst
index 85e80e30160b..d33b554ca7ba 100644
--- a/Documentation/powerpc/index.rst
+++ b/Documentation/powerpc/index.rst
@@ -15,6 +15,7 @@ powerpc
cxl
cxlflash
dawr-power9
+ dexcr
dscr
eeh-pci-error-recovery
elf_hwcaps
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 10/12] selftests/powerpc: Add more utility macros
2023-03-30 5:50 [PATCH v2 00/12] Add static DEXCR support Benjamin Gray
` (8 preceding siblings ...)
2023-03-30 5:50 ` [PATCH v2 09/12] Documentation: Document PowerPC kernel DEXCR interface Benjamin Gray
@ 2023-03-30 5:50 ` Benjamin Gray
2023-05-08 4:43 ` Russell Currey
2023-03-30 5:50 ` [PATCH v2 11/12] selftests/powerpc/dexcr: Add hashst/hashchk test Benjamin Gray
2023-03-30 5:50 ` [PATCH v2 12/12] selftests/powerpc/dexcr: Add DEXCR status utility lsdexcr Benjamin Gray
11 siblings, 1 reply; 23+ messages in thread
From: Benjamin Gray @ 2023-03-30 5:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: npiggin, Benjamin Gray
* Include unistd.h for _exit()
* Include stdio.h for fprintf()
* Adds _MSG assertion variants to provide more context behind why a
failure occurred.
* Move ARRAY_SIZE macro to utils.h
The _MSG variants and ARRAY_SIZE will be used by the following
DEXCR selftests.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
---
v1: * Remove the signal handler variants
* Describe why headers are included
---
.../testing/selftests/powerpc/include/utils.h | 27 ++++++++++++++++++-
.../powerpc/pmu/sampling_tests/misc.h | 2 --
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/tools/testing/selftests/powerpc/include/utils.h b/tools/testing/selftests/powerpc/include/utils.h
index eed7dd7582b2..65b242842ff5 100644
--- a/tools/testing/selftests/powerpc/include/utils.h
+++ b/tools/testing/selftests/powerpc/include/utils.h
@@ -9,11 +9,17 @@
#define __cacheline_aligned __attribute__((aligned(128)))
#include <stdint.h>
+#include <stdio.h>
#include <stdbool.h>
#include <linux/auxvec.h>
#include <linux/perf_event.h>
#include <asm/cputable.h>
#include "reg.h"
+#include <unistd.h>
+
+#ifndef ARRAY_SIZE
+# define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
/* Avoid headaches with PRI?64 - just use %ll? always */
typedef unsigned long long u64;
@@ -64,7 +70,6 @@ struct perf_event_read {
};
#if !defined(__GLIBC_PREREQ) || !__GLIBC_PREREQ(2, 30)
-#include <unistd.h>
#include <sys/syscall.h>
static inline pid_t gettid(void)
@@ -113,6 +118,16 @@ do { \
} \
} while (0)
+#define FAIL_IF_MSG(x, msg) \
+do { \
+ if ((x)) { \
+ fprintf(stderr, \
+ "[FAIL] Test FAILED on line %d: %s\n", \
+ __LINE__, msg); \
+ return 1; \
+ } \
+} while (0)
+
#define FAIL_IF_EXIT(x) \
do { \
if ((x)) { \
@@ -122,6 +137,16 @@ do { \
} \
} while (0)
+#define FAIL_IF_EXIT_MSG(x, msg) \
+do { \
+ if ((x)) { \
+ fprintf(stderr, \
+ "[FAIL] Test FAILED on line %d: %s\n", \
+ __LINE__, msg); \
+ _exit(1); \
+ } \
+} while (0)
+
/* The test harness uses this, yes it's gross */
#define MAGIC_SKIP_RETURN_VALUE 99
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index 4181755cf5a0..64e25cce1435 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -18,8 +18,6 @@
#define MMCR1_RSQ 0x200000000000ULL /* radix scope qual field */
#define BHRB_DISABLE 0x2000000000ULL /* MMCRA BHRB DISABLE bit */
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
extern int ev_mask_pmcxsel, ev_shift_pmcxsel;
extern int ev_mask_marked, ev_shift_marked;
extern int ev_mask_comb, ev_shift_comb;
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 10/12] selftests/powerpc: Add more utility macros
2023-03-30 5:50 ` [PATCH v2 10/12] selftests/powerpc: Add more utility macros Benjamin Gray
@ 2023-05-08 4:43 ` Russell Currey
0 siblings, 0 replies; 23+ messages in thread
From: Russell Currey @ 2023-05-08 4:43 UTC (permalink / raw)
To: Benjamin Gray, linuxppc-dev; +Cc: npiggin
On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote:
> * Include unistd.h for _exit()
> * Include stdio.h for fprintf()
> * Adds _MSG assertion variants to provide more context behind why a
> failure occurred.
> * Move ARRAY_SIZE macro to utils.h
>
> The _MSG variants and ARRAY_SIZE will be used by the following
> DEXCR selftests.
>
> Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
>
I'd prefer if your commit message led with adding FAIL_IF_MSG etc and
then mentioned the other changes to support it. It's unintuitive to
read as-is.
Reviewed-by: Russell Currey <ruscur@russell.cc>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 11/12] selftests/powerpc/dexcr: Add hashst/hashchk test
2023-03-30 5:50 [PATCH v2 00/12] Add static DEXCR support Benjamin Gray
` (9 preceding siblings ...)
2023-03-30 5:50 ` [PATCH v2 10/12] selftests/powerpc: Add more utility macros Benjamin Gray
@ 2023-03-30 5:50 ` Benjamin Gray
2023-03-30 5:50 ` [PATCH v2 12/12] selftests/powerpc/dexcr: Add DEXCR status utility lsdexcr Benjamin Gray
11 siblings, 0 replies; 23+ messages in thread
From: Benjamin Gray @ 2023-03-30 5:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: npiggin, Benjamin Gray
Test the kernel DEXCR[NPHIE] interface and hashchk exception handling.
Introduces with it a DEXCR utils library for common DEXCR operations.
Volatile is used to prevent the compiler optimising away the signal
tests.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
---
v1: * Clean up dexcr makefile
* Include kernel headers in CFLAGS
* Use numeric literals for hashst/hashchk to support older
toolchains
* A lot of other refactoring
---
tools/testing/selftests/powerpc/Makefile | 1 +
.../selftests/powerpc/dexcr/.gitignore | 1 +
.../testing/selftests/powerpc/dexcr/Makefile | 7 +
tools/testing/selftests/powerpc/dexcr/dexcr.c | 132 ++++++++++
tools/testing/selftests/powerpc/dexcr/dexcr.h | 49 ++++
.../selftests/powerpc/dexcr/hashchk_test.c | 227 ++++++++++++++++++
tools/testing/selftests/powerpc/include/reg.h | 4 +
.../testing/selftests/powerpc/include/utils.h | 4 +
tools/testing/selftests/powerpc/utils.c | 24 ++
9 files changed, 449 insertions(+)
create mode 100644 tools/testing/selftests/powerpc/dexcr/.gitignore
create mode 100644 tools/testing/selftests/powerpc/dexcr/Makefile
create mode 100644 tools/testing/selftests/powerpc/dexcr/dexcr.c
create mode 100644 tools/testing/selftests/powerpc/dexcr/dexcr.h
create mode 100644 tools/testing/selftests/powerpc/dexcr/hashchk_test.c
diff --git a/tools/testing/selftests/powerpc/Makefile b/tools/testing/selftests/powerpc/Makefile
index 6ba95cd19e42..00dbd000ee01 100644
--- a/tools/testing/selftests/powerpc/Makefile
+++ b/tools/testing/selftests/powerpc/Makefile
@@ -17,6 +17,7 @@ SUB_DIRS = alignment \
benchmarks \
cache_shape \
copyloops \
+ dexcr \
dscr \
mm \
nx-gzip \
diff --git a/tools/testing/selftests/powerpc/dexcr/.gitignore b/tools/testing/selftests/powerpc/dexcr/.gitignore
new file mode 100644
index 000000000000..d12e4560aca9
--- /dev/null
+++ b/tools/testing/selftests/powerpc/dexcr/.gitignore
@@ -0,0 +1 @@
+hashchk_test
diff --git a/tools/testing/selftests/powerpc/dexcr/Makefile b/tools/testing/selftests/powerpc/dexcr/Makefile
new file mode 100644
index 000000000000..16c8b489948a
--- /dev/null
+++ b/tools/testing/selftests/powerpc/dexcr/Makefile
@@ -0,0 +1,7 @@
+TEST_GEN_PROGS := hashchk_test
+
+include ../../lib.mk
+
+$(OUTPUT)/hashchk_test: CFLAGS += -fno-pie $(call cc-option,-mno-rop-protect)
+
+$(TEST_GEN_PROGS): ../harness.c ../utils.c ./dexcr.c
diff --git a/tools/testing/selftests/powerpc/dexcr/dexcr.c b/tools/testing/selftests/powerpc/dexcr/dexcr.c
new file mode 100644
index 000000000000..65ec5347de98
--- /dev/null
+++ b/tools/testing/selftests/powerpc/dexcr/dexcr.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <errno.h>
+#include <setjmp.h>
+#include <signal.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+
+#include "dexcr.h"
+#include "reg.h"
+#include "utils.h"
+
+static jmp_buf generic_signal_jump_buf;
+
+static void generic_signal_handler(int signum, siginfo_t *info, void *context)
+{
+ longjmp(generic_signal_jump_buf, 0);
+}
+
+bool dexcr_exists(void)
+{
+ struct sigaction old;
+ volatile bool exists;
+
+ old = push_signal_handler(SIGILL, generic_signal_handler);
+ if (setjmp(generic_signal_jump_buf))
+ goto out;
+
+ /*
+ * If the SPR is not recognised by the hardware it triggers
+ * a hypervisor emulation interrupt. If the kernel does not
+ * recognise/try to emulate it, we receive a SIGILL signal.
+ *
+ * If we do not receive a signal, assume we have the SPR or the
+ * kernel is trying to emulate it correctly.
+ */
+ exists = false;
+ mfspr(SPRN_DEXCR_RO);
+ exists = true;
+
+out:
+ pop_signal_handler(SIGILL, old);
+ return exists;
+}
+
+/*
+ * Just test if a bad hashchk triggers a signal, without checking
+ * for support or if the NPHIE aspect is enabled.
+ */
+bool hashchk_triggers(void)
+{
+ struct sigaction old;
+ volatile bool triggers;
+
+ old = push_signal_handler(SIGILL, generic_signal_handler);
+ if (setjmp(generic_signal_jump_buf))
+ goto out;
+
+ triggers = true;
+ do_bad_hashchk();
+ triggers = false;
+
+out:
+ pop_signal_handler(SIGILL, old);
+ return triggers;
+}
+
+unsigned int get_dexcr(enum dexcr_source source)
+{
+ switch (source) {
+ case DEXCR:
+ return mfspr(SPRN_DEXCR_RO);
+ case HDEXCR:
+ return mfspr(SPRN_HDEXCR_RO);
+ case EFFECTIVE:
+ return mfspr(SPRN_DEXCR_RO) | mfspr(SPRN_HDEXCR_RO);
+ default:
+ FAIL_IF_EXIT_MSG(true, "bad enum dexcr_source");
+ }
+}
+
+void await_child_success(pid_t pid)
+{
+ int wstatus;
+
+ FAIL_IF_EXIT_MSG(pid == -1, "fork failed");
+ FAIL_IF_EXIT_MSG(waitpid(pid, &wstatus, 0) == -1, "wait failed");
+ FAIL_IF_EXIT_MSG(!WIFEXITED(wstatus), "child did not exit cleanly");
+ FAIL_IF_EXIT_MSG(WEXITSTATUS(wstatus) != 0, "child exit error");
+}
+
+/*
+ * Perform a hashst instruction. The following components determine the result
+ *
+ * 1. The LR value (any register technically)
+ * 2. The SP value (also any register, but it must be a valid address)
+ * 3. A secret key managed by the kernel
+ *
+ * The result is stored to the address held in SP.
+ */
+void hashst(unsigned long lr, void *sp)
+{
+ asm volatile ("addi 31, %0, 0;" /* set r31 (pretend LR) to lr */
+ "addi 30, %1, 8;" /* set r30 (pretend SP) to sp + 8 */
+ PPC_RAW_HASHST(31, -8, 30) /* compute hash into stack location */
+ : : "r" (lr), "r" (sp) : "r31", "r30", "memory");
+}
+
+/*
+ * Perform a hashchk instruction. A hash is computed as per hashst(),
+ * however the result is not stored to memory. Instead the existing
+ * value is read and compared against the computed hash.
+ *
+ * If they match, execution continues.
+ * If they differ, an interrupt triggers.
+ */
+void hashchk(unsigned long lr, void *sp)
+{
+ asm volatile ("addi 31, %0, 0;" /* set r31 (pretend LR) to lr */
+ "addi 30, %1, 8;" /* set r30 (pretend SP) to sp + 8 */
+ PPC_RAW_HASHCHK(31, -8, 30) /* check hash at stack location */
+ : : "r" (lr), "r" (sp) : "r31", "r30", "memory");
+}
+
+void do_bad_hashchk(void)
+{
+ unsigned long hash = 0;
+
+ hashst(0, &hash);
+ hash += 1;
+ hashchk(0, &hash);
+}
diff --git a/tools/testing/selftests/powerpc/dexcr/dexcr.h b/tools/testing/selftests/powerpc/dexcr/dexcr.h
new file mode 100644
index 000000000000..f55cbbc8643b
--- /dev/null
+++ b/tools/testing/selftests/powerpc/dexcr/dexcr.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * POWER Dynamic Execution Control Facility (DEXCR)
+ *
+ * This header file contains helper functions and macros
+ * required for all the DEXCR related test cases.
+ */
+#ifndef _SELFTESTS_POWERPC_DEXCR_DEXCR_H
+#define _SELFTESTS_POWERPC_DEXCR_DEXCR_H
+
+#include <stdbool.h>
+#include <sys/types.h>
+
+#include "reg.h"
+
+#define DEXCR_PR_BIT(aspect) __MASK(63 - (32 + (aspect)))
+#define DEXCR_PR_SBHE DEXCR_PR_BIT(0)
+#define DEXCR_PR_IBRTPD DEXCR_PR_BIT(3)
+#define DEXCR_PR_SRAPD DEXCR_PR_BIT(4)
+#define DEXCR_PR_NPHIE DEXCR_PR_BIT(5)
+
+#define PPC_RAW_HASH_ARGS(b, i, a) \
+ ((((i) >> 3) & 0x1F) << 21 | (a) << 16 | (b) << 11 | (((i) >> 8) & 0x1))
+#define PPC_RAW_HASHST(b, i, a) \
+ str(.long (0x7C0005A4 | PPC_RAW_HASH_ARGS(b, i, a));)
+#define PPC_RAW_HASHCHK(b, i, a) \
+ str(.long (0x7C0005E4 | PPC_RAW_HASH_ARGS(b, i, a));)
+
+bool dexcr_exists(void);
+
+bool hashchk_triggers(void);
+
+enum dexcr_source {
+ DEXCR, /* Userspace DEXCR value */
+ HDEXCR, /* Hypervisor enforced DEXCR value */
+ EFFECTIVE, /* Bitwise OR of UDEXCR and ENFORCED DEXCR bits */
+};
+
+unsigned int get_dexcr(enum dexcr_source source);
+
+void await_child_success(pid_t pid);
+
+void hashst(unsigned long lr, void *sp);
+
+void hashchk(unsigned long lr, void *sp);
+
+void do_bad_hashchk(void);
+
+#endif /* _SELFTESTS_POWERPC_DEXCR_DEXCR_H */
diff --git a/tools/testing/selftests/powerpc/dexcr/hashchk_test.c b/tools/testing/selftests/powerpc/dexcr/hashchk_test.c
new file mode 100644
index 000000000000..7d5658c9ebe4
--- /dev/null
+++ b/tools/testing/selftests/powerpc/dexcr/hashchk_test.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#define _GNU_SOURCE
+
+#include <errno.h>
+#include <fcntl.h>
+#include <limits.h>
+#include <sched.h>
+#include <setjmp.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <sys/prctl.h>
+#include <unistd.h>
+
+#include "dexcr.h"
+#include "utils.h"
+
+static int require_nphie(void)
+{
+ SKIP_IF_MSG(!dexcr_exists(), "DEXCR not supported");
+ SKIP_IF_MSG(!(get_dexcr(EFFECTIVE) & DEXCR_PR_NPHIE),
+ "DEXCR[NPHIE] not enabled");
+
+ return 0;
+}
+
+static jmp_buf hashchk_detected_buf;
+static const char *hashchk_failure_msg;
+
+static void hashchk_handler(int signum, siginfo_t *info, void *context)
+{
+ if (signum != SIGILL)
+ hashchk_failure_msg = "wrong signal received";
+ else if (info->si_code != ILL_ILLOPN)
+ hashchk_failure_msg = "wrong signal code received";
+
+ longjmp(hashchk_detected_buf, 0);
+}
+
+/*
+ * Check that hashchk triggers when DEXCR[NPHIE] is enabled
+ * and is detected as such by the kernel exception handler
+ */
+static int hashchk_detected_test(void)
+{
+ struct sigaction old;
+ int err;
+
+ err = require_nphie();
+ if (err)
+ return err;
+
+ old = push_signal_handler(SIGILL, hashchk_handler);
+ if (setjmp(hashchk_detected_buf))
+ goto out;
+
+ hashchk_failure_msg = NULL;
+ do_bad_hashchk();
+ hashchk_failure_msg = "hashchk failed to trigger";
+
+out:
+ pop_signal_handler(SIGILL, old);
+ FAIL_IF_MSG(hashchk_failure_msg, hashchk_failure_msg);
+ return 0;
+}
+
+#define HASH_COUNT 8
+
+static unsigned long hash_values[HASH_COUNT + 1];
+
+static void fill_hash_values(void)
+{
+ for (unsigned long i = 0; i < HASH_COUNT; i++)
+ hashst(i, &hash_values[i]);
+
+ /* Used to ensure the checks uses the same addresses as the hashes */
+ hash_values[HASH_COUNT] = (unsigned long)&hash_values;
+}
+
+static unsigned int count_hash_values_matches(void)
+{
+ unsigned long matches = 0;
+
+ for (unsigned long i = 0; i < HASH_COUNT; i++) {
+ unsigned long orig_hash = hash_values[i];
+ hash_values[i] = 0;
+
+ hashst(i, &hash_values[i]);
+
+ if (hash_values[i] == orig_hash)
+ matches++;
+ }
+
+ return matches;
+}
+
+static int hashchk_exec_child(void)
+{
+ ssize_t count;
+
+ fill_hash_values();
+
+ count = write(STDOUT_FILENO, hash_values, sizeof(hash_values));
+ return count == sizeof(hash_values) ? 0 : EOVERFLOW;
+}
+
+static char *hashchk_exec_child_args[] = { "hashchk_exec_child", NULL };
+
+/*
+ * Check that new programs get different keys so a malicious process
+ * can't recreate a victim's hash values.
+ */
+static int hashchk_exec_random_key_test(void)
+{
+ pid_t pid;
+ int err;
+ int pipefd[2];
+
+ err = require_nphie();
+ if (err)
+ return err;
+
+ FAIL_IF_MSG(pipe(pipefd), "failed to create pipe");
+
+ pid = fork();
+ if (pid == 0) {
+ if (dup2(pipefd[1], STDOUT_FILENO) == -1)
+ _exit(errno);
+
+ execve("/proc/self/exe", hashchk_exec_child_args, NULL);
+ _exit(errno);
+ }
+
+ await_child_success(pid);
+ FAIL_IF_MSG(read(pipefd[0], hash_values, sizeof(hash_values)) != sizeof(hash_values),
+ "missing expected child output");
+
+ /* Verify the child used the same hash_values address */
+ FAIL_IF_EXIT_MSG(hash_values[HASH_COUNT] != (unsigned long)&hash_values,
+ "bad address check");
+
+ /* If all hashes are the same it means (most likely) same key */
+ FAIL_IF_MSG(count_hash_values_matches() == HASH_COUNT, "shared key detected");
+
+ return 0;
+}
+
+/*
+ * Check that forks share the same key so that existing hash values
+ * remain valid.
+ */
+static int hashchk_fork_share_key_test(void)
+{
+ pid_t pid;
+ int err;
+
+ err = require_nphie();
+ if (err)
+ return err;
+
+ fill_hash_values();
+
+ pid = fork();
+ if (pid == 0) {
+ if (count_hash_values_matches() != HASH_COUNT)
+ _exit(1);
+ _exit(0);
+ }
+
+ await_child_success(pid);
+ return 0;
+}
+
+#define STACK_SIZE (1024 * 1024)
+
+static int hashchk_clone_child_fn(void *args)
+{
+ fill_hash_values();
+ return 0;
+}
+
+/*
+ * Check that threads share the same key so that existing hash values
+ * remain valid.
+ */
+static int hashchk_clone_share_key_test(void)
+{
+ void *child_stack;
+ pid_t pid;
+ int err;
+
+ err = require_nphie();
+ if (err)
+ return err;
+
+ child_stack = mmap(NULL, STACK_SIZE, PROT_READ | PROT_WRITE,
+ MAP_PRIVATE | MAP_ANONYMOUS | MAP_STACK, -1, 0);
+
+ FAIL_IF_MSG(child_stack == MAP_FAILED, "failed to map child stack");
+
+ pid = clone(hashchk_clone_child_fn, child_stack + STACK_SIZE,
+ CLONE_VM | SIGCHLD, NULL);
+
+ await_child_success(pid);
+ FAIL_IF_MSG(count_hash_values_matches() != HASH_COUNT,
+ "different key detected");
+
+ return 0;
+}
+
+int main(int argc, char *argv[])
+{
+ int err = 0;
+
+ if (argc >= 1 && !strcmp(argv[0], hashchk_exec_child_args[0]))
+ return hashchk_exec_child();
+
+ err |= test_harness(hashchk_detected_test, "hashchk_detected");
+ err |= test_harness(hashchk_exec_random_key_test, "hashchk_exec_random_key");
+ err |= test_harness(hashchk_fork_share_key_test, "hashchk_fork_share_key");
+ err |= test_harness(hashchk_clone_share_key_test, "hashchk_clone_share_key");
+
+ return err;
+}
diff --git a/tools/testing/selftests/powerpc/include/reg.h b/tools/testing/selftests/powerpc/include/reg.h
index d5a547f72669..fad09c9d3387 100644
--- a/tools/testing/selftests/powerpc/include/reg.h
+++ b/tools/testing/selftests/powerpc/include/reg.h
@@ -19,6 +19,8 @@
#define mb() asm volatile("sync" : : : "memory");
#define barrier() asm volatile("" : : : "memory");
+#define SPRN_HDEXCR_RO 455 /* Userspace readonly view of SPRN_HDEXCR (471) */
+
#define SPRN_MMCR2 769
#define SPRN_MMCRA 770
#define SPRN_MMCR0 779
@@ -47,6 +49,8 @@
#define SPRN_SDAR 781
#define SPRN_SIER 768
+#define SPRN_DEXCR_RO 812 /* Userspace readonly view of SPRN_DEXCR (828) */
+
#define SPRN_TEXASR 0x82 /* Transaction Exception and Status Register */
#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
diff --git a/tools/testing/selftests/powerpc/include/utils.h b/tools/testing/selftests/powerpc/include/utils.h
index 65b242842ff5..85fa6fdbeafa 100644
--- a/tools/testing/selftests/powerpc/include/utils.h
+++ b/tools/testing/selftests/powerpc/include/utils.h
@@ -11,6 +11,7 @@
#include <stdint.h>
#include <stdio.h>
#include <stdbool.h>
+#include <sys/signal.h>
#include <linux/auxvec.h>
#include <linux/perf_event.h>
#include <asm/cputable.h>
@@ -108,6 +109,9 @@ static inline char *auxv_platform(void)
bool is_ppc64le(void);
int using_hash_mmu(bool *using_hash);
+struct sigaction push_signal_handler(int sig, void (*fn)(int, siginfo_t *, void *));
+struct sigaction pop_signal_handler(int sig, struct sigaction old_handler);
+
/* Yes, this is evil */
#define FAIL_IF(x) \
do { \
diff --git a/tools/testing/selftests/powerpc/utils.c b/tools/testing/selftests/powerpc/utils.c
index 7c8cfedb012a..b1d01a10f143 100644
--- a/tools/testing/selftests/powerpc/utils.c
+++ b/tools/testing/selftests/powerpc/utils.c
@@ -595,3 +595,27 @@ int using_hash_mmu(bool *using_hash)
fclose(f);
return rc;
}
+
+struct sigaction push_signal_handler(int sig, void (*fn)(int, siginfo_t *, void *))
+{
+ struct sigaction sa;
+ struct sigaction old_handler;
+
+ sa.sa_sigaction = fn;
+ sigemptyset(&sa.sa_mask);
+ sa.sa_flags = SA_SIGINFO;
+ FAIL_IF_EXIT_MSG(sigaction(sig, &sa, &old_handler),
+ "failed to push signal handler");
+
+ return old_handler;
+}
+
+struct sigaction pop_signal_handler(int sig, struct sigaction old_handler)
+{
+ struct sigaction popped;
+
+ FAIL_IF_EXIT_MSG(sigaction(sig, &old_handler, &popped),
+ "failed to pop signal handler");
+
+ return popped;
+}
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 12/12] selftests/powerpc/dexcr: Add DEXCR status utility lsdexcr
2023-03-30 5:50 [PATCH v2 00/12] Add static DEXCR support Benjamin Gray
` (10 preceding siblings ...)
2023-03-30 5:50 ` [PATCH v2 11/12] selftests/powerpc/dexcr: Add hashst/hashchk test Benjamin Gray
@ 2023-03-30 5:50 ` Benjamin Gray
11 siblings, 0 replies; 23+ messages in thread
From: Benjamin Gray @ 2023-03-30 5:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: npiggin, Benjamin Gray
Add a utility 'lsdexcr' to print the current DEXCR status. Useful for
quickly checking the status such as when debugging test failures or
verifying the new default DEXCR does what you want (for userspace at
least). Example output:
# ./lsdexcr
uDEXCR: 04000000 (NPHIE)
HDEXCR: 00000000
Effective: 04000000 (NPHIE)
SBHE (0): clear (Speculative branch hint enable)
IBRTPD (3): clear (Indirect branch recurrent target ...)
SRAPD (4): clear (Subroutine return address ...)
NPHIE * (5): set (Non-privileged hash instruction enable)
PHIE (6): clear (Privileged hash instruction enable)
DEXCR[NPHIE] enabled: hashst/hashchk working
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
---
v1: * Report if hashst/hashchk actually does something
---
.../selftests/powerpc/dexcr/.gitignore | 1 +
.../testing/selftests/powerpc/dexcr/Makefile | 2 +
.../testing/selftests/powerpc/dexcr/lsdexcr.c | 141 ++++++++++++++++++
3 files changed, 144 insertions(+)
create mode 100644 tools/testing/selftests/powerpc/dexcr/lsdexcr.c
diff --git a/tools/testing/selftests/powerpc/dexcr/.gitignore b/tools/testing/selftests/powerpc/dexcr/.gitignore
index d12e4560aca9..b82f45dd46b9 100644
--- a/tools/testing/selftests/powerpc/dexcr/.gitignore
+++ b/tools/testing/selftests/powerpc/dexcr/.gitignore
@@ -1 +1,2 @@
hashchk_test
+lsdexcr
diff --git a/tools/testing/selftests/powerpc/dexcr/Makefile b/tools/testing/selftests/powerpc/dexcr/Makefile
index 16c8b489948a..76210f2bcec3 100644
--- a/tools/testing/selftests/powerpc/dexcr/Makefile
+++ b/tools/testing/selftests/powerpc/dexcr/Makefile
@@ -1,7 +1,9 @@
TEST_GEN_PROGS := hashchk_test
+TEST_GEN_FILES := lsdexcr
include ../../lib.mk
$(OUTPUT)/hashchk_test: CFLAGS += -fno-pie $(call cc-option,-mno-rop-protect)
$(TEST_GEN_PROGS): ../harness.c ../utils.c ./dexcr.c
+$(TEST_GEN_FILES): ../utils.c ./dexcr.c
diff --git a/tools/testing/selftests/powerpc/dexcr/lsdexcr.c b/tools/testing/selftests/powerpc/dexcr/lsdexcr.c
new file mode 100644
index 000000000000..94abbfcc389e
--- /dev/null
+++ b/tools/testing/selftests/powerpc/dexcr/lsdexcr.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <errno.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "dexcr.h"
+#include "utils.h"
+
+static unsigned int dexcr;
+static unsigned int hdexcr;
+static unsigned int effective;
+
+struct dexcr_aspect {
+ const char *name;
+ const char *desc;
+ unsigned int index;
+};
+
+static const struct dexcr_aspect aspects[] = {
+ {
+ .name = "SBHE",
+ .desc = "Speculative branch hint enable",
+ .index = 0,
+ },
+ {
+ .name = "IBRTPD",
+ .desc = "Indirect branch recurrent target prediction disable",
+ .index = 3,
+ },
+ {
+ .name = "SRAPD",
+ .desc = "Subroutine return address prediction disable",
+ .index = 4,
+ },
+ {
+ .name = "NPHIE",
+ .desc = "Non-privileged hash instruction enable",
+ .index = 5,
+ },
+ {
+ .name = "PHIE",
+ .desc = "Privileged hash instruction enable",
+ .index = 6,
+ },
+};
+
+static void print_list(const char *list[], size_t len)
+{
+ for (size_t i = 0; i < len; i++) {
+ printf("%s", list[i]);
+ if (i + 1 < len)
+ printf(", ");
+ }
+}
+
+static void print_dexcr(char *name, unsigned int bits)
+{
+ const char *enabled_aspects[ARRAY_SIZE(aspects) + 1] = {NULL};
+ size_t j = 0;
+
+ printf("%s: %08x", name, bits);
+
+ if (bits == 0) {
+ printf("\n");
+ return;
+ }
+
+ for (size_t i = 0; i < ARRAY_SIZE(aspects); i++) {
+ unsigned int mask = DEXCR_PR_BIT(aspects[i].index);
+
+ if (bits & mask) {
+ enabled_aspects[j++] = aspects[i].name;
+ bits &= ~mask;
+ }
+ }
+
+ if (bits)
+ enabled_aspects[j++] = "unknown";
+
+ printf(" (");
+ print_list(enabled_aspects, j);
+ printf(")\n");
+}
+
+static void print_aspect(const struct dexcr_aspect *aspect)
+{
+ const char *attributes[8] = {NULL};
+ size_t j = 0;
+ unsigned long mask;
+
+ mask = DEXCR_PR_BIT(aspect->index);
+ if (dexcr & mask)
+ attributes[j++] = "set";
+ if (hdexcr & mask)
+ attributes[j++] = "set (hypervisor)";
+ if (!(effective & mask))
+ attributes[j++] = "clear";
+
+ printf("%12s %c (%d): ", aspect->name, effective & mask ? '*' : ' ', aspect->index);
+ print_list(attributes, j);
+ printf(" \t(%s)\n", aspect->desc);
+}
+
+int main(int argc, char *argv[])
+{
+ if (!dexcr_exists()) {
+ printf("DEXCR not detected on this hardware\n");
+ return 1;
+ }
+
+ dexcr = get_dexcr(DEXCR);
+ hdexcr = get_dexcr(HDEXCR);
+ effective = dexcr | hdexcr;
+
+ print_dexcr(" DEXCR", dexcr);
+ print_dexcr(" HDEXCR", hdexcr);
+ print_dexcr("Effective", effective);
+ printf("\n");
+
+ for (size_t i = 0; i < ARRAY_SIZE(aspects); i++)
+ print_aspect(&aspects[i]);
+ printf("\n");
+
+ if (effective & DEXCR_PR_NPHIE) {
+ printf("DEXCR[NPHIE] enabled: hashst/hashchk ");
+ if (hashchk_triggers())
+ printf("working\n");
+ else
+ printf("failed to trigger\n");
+ } else {
+ printf("DEXCR[NPHIE] disabled: hashst/hashchk ");
+ if (hashchk_triggers())
+ printf("unexpectedly triggered\n");
+ else
+ printf("ignored\n");
+ }
+
+ return 0;
+}
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread