From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0EDD6C77B73 for ; Sat, 6 May 2023 07:59:45 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4QD0ML3vb1z3fHR for ; Sat, 6 May 2023 17:59:42 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=NQRCz43C; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linaro.org (client-ip=2607:f8b0:4864:20::42e; helo=mail-pf1-x42e.google.com; envelope-from=manivannan.sadhasivam@linaro.org; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=NQRCz43C; dkim-atps=neutral Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4QD0LL35nzz3bpn for ; Sat, 6 May 2023 17:58:47 +1000 (AEST) Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-643b60855c8so506157b3a.2 for ; Sat, 06 May 2023 00:58:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683359925; x=1685951925; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=9N1rc/5Fi1FR3PRXTb19F/ZGifHjTtA2q2Cae30+mlA=; b=NQRCz43CT3Am3q/I02DZVA0uqVsD/A7hjEDQjanb1XYTXvdhgJhATgrvGC/pEKtZ53 czw2fdaLr3ZB76Bw6/1H9YubH2IK2ap/hVjLZcCwc/Bs75xT96EizfONWjqYhcfQUGXl lwraI32bJREv8kOJ2O8aNUuSAN2Npeh9AFDoCzk6Nlrl4/YOkHEEPkdab4MOEyVV13gA pmRSW3ebFAApIF65wN8wyLf6i/mlBP2PvkqKZPsRG6iXzCyGZPKW9aKEANwVLl3jNrBy J2m0/s23etfyiSjR/Cbz+ylvBLzFaJBuHXbotkrFPdknOMrr4M6Na5Hoo2hysHuhtF81 kgLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683359925; x=1685951925; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=9N1rc/5Fi1FR3PRXTb19F/ZGifHjTtA2q2Cae30+mlA=; b=iRk62Ka8kvgrVBWgBgT/+8tA7ILd6RpS6R+I8mULJMW+orL+pPysFix7WGi5sdLTtC 5/XfcUD3Dr38niXqArxjNqSYeyUbAPw24iyWGX3IP4g2aIHYFAR0wH24YquGs1Btiwr7 hYE/fhPKXz9/LUQZQNNCkbsCRbC+PKbd/LdulepeaVqcj1C3Xh7Aqx3HE67kJAOst6Kc kOy7etmeas59qGKeGRd1Q6tG9x4HWlkSUrYzgWhzQV00L0B7fBRrt0CvbqTvOTYcTcLA HKnRGxBdpIIWKfSCo4jagBmsP82eoQ78GMvmLhSwzdTeHFZhohlGCTXESCoGkKsMFHZT vkCA== X-Gm-Message-State: AC+VfDyQqYHYFCORBX0a/QeHeH/dOuAd4+bcUM5Xvkr4TlKTOyMBKHxA AGTqqfeublloKcoQu8O2oHJq X-Google-Smtp-Source: ACHHUZ6s1Jzex0YPfLJUb6h3oibL3F+U2pv0j40QoSsQ4BhKF3WctKGX8jpyOyBkUm482uYZcTvusw== X-Received: by 2002:a05:6a00:1686:b0:643:a35d:b8dc with SMTP id k6-20020a056a00168600b00643a35db8dcmr5053349pfc.28.1683359924874; Sat, 06 May 2023 00:58:44 -0700 (PDT) Received: from thinkpad ([120.138.12.87]) by smtp.gmail.com with ESMTPSA id h16-20020aa786d0000000b0063b8f33cb81sm2728451pfo.93.2023.05.06.00.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:58:44 -0700 (PDT) Date: Sat, 6 May 2023 13:28:37 +0530 From: Manivannan Sadhasivam To: Frank Li Subject: Re: [PATCH v2 1/1] PCI: layerscape: Add the endpoint linkup notifier support Message-ID: <20230506075837.GA9238@thinkpad> References: <20230501144807.1616244-1-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230501144807.1616244-1-Frank.Li@nxp.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , imx@lists.linux.dev, Rob Herring , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , Lorenzo Pieralisi , open list , Minghuan Lian , "moderated list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , Roy Zang , Bjorn Helgaas , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , Mingkai Hu Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, May 01, 2023 at 10:48:06AM -0400, Frank Li wrote: > Layerscape has PME interrupt, which can be used as linkup notifier. > Set CFG_READY bit when linkup detected. Where are you setting this bit? > > Signed-off-by: Xiaowei Bao > Signed-off-by: Frank Li > --- > Change from v1 to v2 > - pme -> PME > - irq -> IRQ > - update dev_info message according to Bjorn's suggestion > - remove '.' at error message > > .../pci/controller/dwc/pci-layerscape-ep.c | 104 +++++++++++++++++- > 1 file changed, 103 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c > index c640db60edc6..e974fbe3b6d8 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c > @@ -18,6 +18,20 @@ > > #include "pcie-designware.h" > > +#define PEX_PF0_CONFIG 0xC0014 > +#define PEX_PF0_CFG_READY BIT(0) > + > +/* PEX PFa PCIE PME and message interrupt registers*/ > +#define PEX_PF0_PME_MES_DR 0xC0020 > +#define PEX_PF0_PME_MES_DR_LUD BIT(7) > +#define PEX_PF0_PME_MES_DR_LDD BIT(9) > +#define PEX_PF0_PME_MES_DR_HRD BIT(10) > + > +#define PEX_PF0_PME_MES_IER 0xC0028 > +#define PEX_PF0_PME_MES_IER_LUDIE BIT(7) > +#define PEX_PF0_PME_MES_IER_LDDIE BIT(9) > +#define PEX_PF0_PME_MES_IER_HRDIE BIT(10) > + > #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev) > > struct ls_pcie_ep_drvdata { > @@ -30,8 +44,88 @@ struct ls_pcie_ep { > struct dw_pcie *pci; > struct pci_epc_features *ls_epc; > const struct ls_pcie_ep_drvdata *drvdata; > + bool big_endian; > + int irq; > }; > > +static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset) > +{ > + struct dw_pcie *pci = pcie->pci; > + > + if (pcie->big_endian) > + return ioread32be(pci->dbi_base + offset); > + else > + return ioread32(pci->dbi_base + offset); > +} > + > +static void ls_lut_writel(struct ls_pcie_ep *pcie, u32 offset, > + u32 value) Above function argument could be wrapped within 80 columns. > +{ > + struct dw_pcie *pci = pcie->pci; > + > + if (pcie->big_endian) > + iowrite32be(value, pci->dbi_base + offset); > + else > + iowrite32(value, pci->dbi_base + offset); > +} > + > +static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) > +{ > + struct ls_pcie_ep *pcie = (struct ls_pcie_ep *)dev_id; No need to do explicit typecase for void pointer. > + struct dw_pcie *pci = pcie->pci; > + u32 val, cfg; > + > + val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); > + if (!val) > + return IRQ_NONE; > + > + if (val & PEX_PF0_PME_MES_DR_LUD) { > + cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); > + cfg |= PEX_PF0_CFG_READY; > + ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); > + dw_pcie_ep_linkup(&pci->ep); > + > + dev_info(pci->dev, "Link up\n"); These messages could be demoted to dev_dbg() logs. > + } else if (val & PEX_PF0_PME_MES_DR_LDD) { > + dev_info(pci->dev, "Link down\n"); > + } else if (val & PEX_PF0_PME_MES_DR_HRD) { > + dev_info(pci->dev, "Hot reset\n"); > + } > + > + ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); You should clear the interrupts before processing. > + > + return IRQ_HANDLED; > +} > + > +static int ls_pcie_ep_interrupt_init(struct ls_pcie_ep *pcie, > + struct platform_device *pdev) > +{ > + u32 val; > + int ret; > + > + pcie->irq = platform_get_irq_byname(pdev, "pme"); > + if (pcie->irq < 0) { > + dev_err(&pdev->dev, "Can't get 'pme' IRQ\n"); PME > + return pcie->irq; > + } > + > + ret = devm_request_irq(&pdev->dev, pcie->irq, > + ls_pcie_ep_event_handler, IRQF_SHARED, > + pdev->name, pcie); Again, please wrap to fit the 80 column width. > + if (ret) { > + dev_err(&pdev->dev, "Can't register PCIe IRQ\n"); > + return ret; > + } > + > + /* Enable interrupts */ > + val = ls_lut_readl(pcie, PEX_PF0_PME_MES_IER); > + val |= PEX_PF0_PME_MES_IER_LDDIE | PEX_PF0_PME_MES_IER_HRDIE | > + PEX_PF0_PME_MES_IER_LUDIE; > + ls_lut_writel(pcie, PEX_PF0_PME_MES_IER, val); > + > + return 0; > +} > + > static const struct pci_epc_features* > ls_pcie_ep_get_features(struct dw_pcie_ep *ep) > { > @@ -125,6 +219,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) > struct ls_pcie_ep *pcie; > struct pci_epc_features *ls_epc; > struct resource *dbi_base; > + int ret; > > pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); > if (!pcie) > @@ -144,6 +239,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) > pci->ops = pcie->drvdata->dw_pcie_ops; > > ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4); > + ls_epc->linkup_notifier = true; > > pcie->pci = pci; > pcie->ls_epc = ls_epc; > @@ -155,9 +251,15 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) > > pci->ep.ops = &ls_pcie_ep_ops; > > + pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); > + > platform_set_drvdata(pdev, pcie); > > - return dw_pcie_ep_init(&pci->ep); > + ret = dw_pcie_ep_init(&pci->ep); > + if (ret) > + return ret; Double space after return. > + > + return ls_pcie_ep_interrupt_init(pcie, pdev); Double space after return. - Mani > } > > static struct platform_driver ls_pcie_ep_driver = { > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்