From: Benjamin Gray <bgray@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org
Cc: Benjamin Gray <bgray@linux.ibm.com>,
ajd@linux.ibm.com, npiggin@gmail.com, ruscur@russell.cc
Subject: [PATCH v3 04/12] powerpc/dexcr: Handle hashchk exception
Date: Fri, 19 May 2023 15:02:28 +1000 [thread overview]
Message-ID: <20230519050236.144847-5-bgray@linux.ibm.com> (raw)
In-Reply-To: <20230519050236.144847-1-bgray@linux.ibm.com>
Recognise and pass the appropriate signal to the user program when a
hashchk instruction triggers. This is independent of allowing
configuration of DEXCR[NPHIE], as a hypervisor can enforce this aspect
regardless of the kernel.
The signal mirrors how ARM reports their similar check failure. For
example, their FPAC handler in arch/arm64/kernel/traps.c do_el0_fpac()
does this. When we fail to read the instruction that caused the fault
we send a segfault, similar to how emulate_math() does it.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
---
v3: * Inline hashchk detection, remove dexcr.c and associated files
v1: * Refactor the hashchk check to return 0 on success, an error
code on failure. Determine what to do based on specific error
code.
* Motivate signal and code
---
arch/powerpc/include/asm/ppc-opcode.h | 1 +
arch/powerpc/kernel/traps.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index ca5a0da7df4e..ef6972aa33b9 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -222,6 +222,7 @@
#define OP_31_XOP_STFSX 663
#define OP_31_XOP_STFSUX 695
#define OP_31_XOP_STFDX 727
+#define OP_31_XOP_HASHCHK 754
#define OP_31_XOP_STFDUX 759
#define OP_31_XOP_LHBRX 790
#define OP_31_XOP_LFIWAX 855
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 9bdd79aa51cf..e59ec6d32d37 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1516,6 +1516,22 @@ static void do_program_check(struct pt_regs *regs)
return;
}
}
+
+ if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE) && user_mode(regs)) {
+ ppc_inst_t insn;
+
+ if (get_user_instr(insn, (void __user *)regs->nip)) {
+ _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
+ return;
+ }
+
+ if (ppc_inst_primary_opcode(insn) == 31 &&
+ get_xop(ppc_inst_val(insn)) == OP_31_XOP_HASHCHK) {
+ _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
+ return;
+ }
+ }
+
_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
return;
}
--
2.40.1
next prev parent reply other threads:[~2023-05-19 5:04 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-19 5:02 [PATCH v3 00/12] Add static DEXCR support Benjamin Gray
2023-05-19 5:02 ` [PATCH v3 01/12] powerpc/book3s: Add missing <linux/sched.h> include Benjamin Gray
2023-05-23 6:45 ` Andrew Donnellan
2023-05-19 5:02 ` [PATCH v3 02/12] powerpc/ptrace: Add missing <linux/regset.h> include Benjamin Gray
2023-05-23 6:51 ` Andrew Donnellan
2023-05-19 5:02 ` [PATCH v3 03/12] powerpc/dexcr: Add initial Dynamic Execution Control Register (DEXCR) support Benjamin Gray
2023-05-19 5:02 ` Benjamin Gray [this message]
2023-05-19 5:02 ` [PATCH v3 05/12] powerpc/dexcr: Support userspace ROP protection Benjamin Gray
2023-05-19 5:02 ` [PATCH v3 06/12] powerpc/dexcr: Support custom default DEXCR value Benjamin Gray
2023-05-19 5:02 ` [PATCH v3 07/12] powerpc/ptrace: Expose DEXCR and HDEXCR registers to ptrace Benjamin Gray
2023-05-19 5:02 ` [PATCH v3 08/12] powerpc/ptrace: Expose HASHKEYR register " Benjamin Gray
2023-05-19 5:02 ` [PATCH v3 09/12] Documentation: Document PowerPC kernel DEXCR interface Benjamin Gray
2023-05-19 5:02 ` [PATCH v3 10/12] selftests/powerpc: Add more utility macros Benjamin Gray
2023-05-19 5:02 ` [PATCH v3 11/12] selftests/powerpc/dexcr: Add hashst/hashchk test Benjamin Gray
2023-05-19 5:02 ` [PATCH v3 12/12] selftests/powerpc/dexcr: Add DEXCR status utility lsdexcr Benjamin Gray
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