From: Nicholas Piggin <npiggin@gmail.com>
To: linuxppc-dev@lists.ozlabs.org
Cc: Nicholas Piggin <npiggin@gmail.com>
Subject: [PATCH 1/4] powerpc: Make mmiowb a wmb
Date: Fri, 9 Jun 2023 20:00:23 +1000 [thread overview]
Message-ID: <20230609100026.8946-1-npiggin@gmail.com> (raw)
mmiowb must ensure MMIO stores inside a spin lock critical section on
one CPU will not be seen by the device after another CPU takes the
same lock and performs MMIOs.
This just requires cache inhibited stores to be ordered with the store
to unlock the spinlock, so wmb() can be used.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/mmiowb.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/mmiowb.h b/arch/powerpc/include/asm/mmiowb.h
index 74a00127eb20..cd071fb97eba 100644
--- a/arch/powerpc/include/asm/mmiowb.h
+++ b/arch/powerpc/include/asm/mmiowb.h
@@ -9,7 +9,7 @@
#include <asm/paca.h>
#define arch_mmiowb_state() (&local_paca->mmiowb_state)
-#define mmiowb() mb()
+#define mmiowb() wmb()
#endif /* CONFIG_MMIOWB */
--
2.40.1
next reply other threads:[~2023-06-09 10:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-09 10:00 Nicholas Piggin [this message]
2023-06-09 10:00 ` [PATCH 2/4] powerpc/64s: Add POWER10 store sync mnemonics Nicholas Piggin
2023-06-13 5:31 ` Joel Stanley
2023-06-14 5:31 ` Nicholas Piggin
2023-06-09 10:00 ` [PATCH 3/4] powerpc/64s: Use stncisync instruction for smp_wmb() when available Nicholas Piggin
2023-06-09 10:00 ` [PATCH 4/4] powerpc/64s: Use POWER10 stsync barrier for wmb() Nicholas Piggin
2023-06-13 13:59 ` Michael Ellerman
2023-06-14 5:56 ` Michael Ellerman
2023-06-15 1:53 ` Nicholas Piggin
2023-06-15 3:09 ` Michael Ellerman
2023-08-24 12:11 ` Michael Ellerman
2023-08-24 12:12 ` Michael Ellerman
2023-08-25 0:28 ` Joel Stanley
2023-08-25 6:59 ` Michael Ellerman
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