* [PATCH v2 1/2] PCI: layerscape: Add support for Link down notification @ 2023-07-18 18:21 Frank Li 2023-07-18 18:21 ` [PATCH v2 2/2] PCI: layerscape: Add the workaround for lost link capablities during reset Frank Li 0 siblings, 1 reply; 3+ messages in thread From: Frank Li @ 2023-07-18 18:21 UTC (permalink / raw) To: mani Cc: imx, kw, linux-pci, lpieralisi, Frank.Li, linux-kernel, minghuan.Lian, mingkai.hu, roy.zang, bhelgaas, linuxppc-dev, robh, linux-arm-kernel Add support to pass Link down notification to Endpoint function driver so that the LINK_DOWN event can be processed by the function. Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> --- Change from v1 to v2 - move pci_epc_linkdown() after dev_dbg() drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index de4c1758a6c3..e0969ff2ddf7 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -89,6 +89,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) dev_dbg(pci->dev, "Link up\n"); } else if (val & PEX_PF0_PME_MES_DR_LDD) { dev_dbg(pci->dev, "Link down\n"); + pci_epc_linkdown(pci->ep.epc); } else if (val & PEX_PF0_PME_MES_DR_HRD) { dev_dbg(pci->dev, "Hot reset\n"); } -- 2.34.1 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v2 2/2] PCI: layerscape: Add the workaround for lost link capablities during reset 2023-07-18 18:21 [PATCH v2 1/2] PCI: layerscape: Add support for Link down notification Frank Li @ 2023-07-18 18:21 ` Frank Li 2023-07-19 4:29 ` Manivannan Sadhasivam 0 siblings, 1 reply; 3+ messages in thread From: Frank Li @ 2023-07-18 18:21 UTC (permalink / raw) To: mani Cc: imx, kw, linux-pci, lpieralisi, Frank.Li, linux-kernel, minghuan.Lian, mingkai.hu, roy.zang, bhelgaas, linuxppc-dev, robh, linux-arm-kernel From: Xiaowei Bao <xiaowei.bao@nxp.com> A workaround for the issue where the PCI Express Endpoint (EP) controller loses the values of the Maximum Link Width and Supported Link Speed from the Link Capabilities Register, which initially configured by the Reset Configuration Word (RCW) during a link-down or hot reset event. Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support") Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> --- change from v1 to v2: - add comments at restore register - add fixes tag .../pci/controller/dwc/pci-layerscape-ep.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index e0969ff2ddf7..b1faf41a2fae 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -45,6 +45,7 @@ struct ls_pcie_ep { struct pci_epc_features *ls_epc; const struct ls_pcie_ep_drvdata *drvdata; int irq; + u32 lnkcap; bool big_endian; }; @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) struct ls_pcie_ep *pcie = dev_id; struct dw_pcie *pci = pcie->pci; u32 val, cfg; + u8 offset; val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); @@ -81,6 +83,19 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) return IRQ_NONE; if (val & PEX_PF0_PME_MES_DR_LUD) { + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + /* + * The values of the Maximum Link Width and Supported Link + * Speed from the Link Capabilities Register will be lost + * during link down or hot reset. Restore initial value + * that configured by the Reset Configuration Word (RCW). + */ + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); + dw_pcie_dbi_ro_wr_dis(pci); + cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); cfg |= PEX_PF0_CFG_READY; ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); @@ -216,6 +231,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) struct ls_pcie_ep *pcie; struct pci_epc_features *ls_epc; struct resource *dbi_base; + u8 offset; int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); @@ -252,6 +268,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + ret = dw_pcie_ep_init(&pci->ep); if (ret) return ret; -- 2.34.1 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2 2/2] PCI: layerscape: Add the workaround for lost link capablities during reset 2023-07-18 18:21 ` [PATCH v2 2/2] PCI: layerscape: Add the workaround for lost link capablities during reset Frank Li @ 2023-07-19 4:29 ` Manivannan Sadhasivam 0 siblings, 0 replies; 3+ messages in thread From: Manivannan Sadhasivam @ 2023-07-19 4:29 UTC (permalink / raw) To: Frank Li Cc: imx, kw, linux-pci, lpieralisi, linux-kernel, minghuan.Lian, mingkai.hu, roy.zang, bhelgaas, linuxppc-dev, robh, linux-arm-kernel On Tue, Jul 18, 2023 at 02:21:42PM -0400, Frank Li wrote: > From: Xiaowei Bao <xiaowei.bao@nxp.com> > > A workaround for the issue where the PCI Express Endpoint (EP) controller > loses the values of the Maximum Link Width and Supported Link Speed from > the Link Capabilities Register, which initially configured by the Reset > Configuration Word (RCW) during a link-down or hot reset event. > > Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support") > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> - Mani > --- > change from v1 to v2: > - add comments at restore register > - add fixes tag > > .../pci/controller/dwc/pci-layerscape-ep.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c > index e0969ff2ddf7..b1faf41a2fae 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c > @@ -45,6 +45,7 @@ struct ls_pcie_ep { > struct pci_epc_features *ls_epc; > const struct ls_pcie_ep_drvdata *drvdata; > int irq; > + u32 lnkcap; > bool big_endian; > }; > > @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) > struct ls_pcie_ep *pcie = dev_id; > struct dw_pcie *pci = pcie->pci; > u32 val, cfg; > + u8 offset; > > val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); > ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); > @@ -81,6 +83,19 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) > return IRQ_NONE; > > if (val & PEX_PF0_PME_MES_DR_LUD) { > + > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + > + /* > + * The values of the Maximum Link Width and Supported Link > + * Speed from the Link Capabilities Register will be lost > + * during link down or hot reset. Restore initial value > + * that configured by the Reset Configuration Word (RCW). > + */ > + dw_pcie_dbi_ro_wr_en(pci); > + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); > + dw_pcie_dbi_ro_wr_dis(pci); > + > cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); > cfg |= PEX_PF0_CFG_READY; > ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); > @@ -216,6 +231,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) > struct ls_pcie_ep *pcie; > struct pci_epc_features *ls_epc; > struct resource *dbi_base; > + u8 offset; > int ret; > > pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); > @@ -252,6 +268,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) > > platform_set_drvdata(pdev, pcie); > > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > + > ret = dw_pcie_ep_init(&pci->ep); > if (ret) > return ret; > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-07-19 4:30 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-07-18 18:21 [PATCH v2 1/2] PCI: layerscape: Add support for Link down notification Frank Li 2023-07-18 18:21 ` [PATCH v2 2/2] PCI: layerscape: Add the workaround for lost link capablities during reset Frank Li 2023-07-19 4:29 ` Manivannan Sadhasivam
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