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From: Andrew Jones <ajones@ventanamicro.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: linux-serial@vger.kernel.org, kvm@vger.kernel.org,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Atish Patra <atishp@atishpatra.org>,
	linuxppc-dev@lists.ozlabs.org, Conor Dooley <conor@kernel.org>,
	linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@dabbelt.com>,
	kvm-riscv@lists.infradead.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	linux-riscv@lists.infradead.org,
	Jiri Slaby <jirislaby@kernel.org>
Subject: Re: [PATCH v2 4/8] RISC-V: KVM: Forward SBI DBCN extension to user-space
Date: Thu, 19 Oct 2023 10:01:53 +0200	[thread overview]
Message-ID: <20231019-5e79c16a0731f60d862ddfff@orel> (raw)
In-Reply-To: <20231012051509.738750-5-apatel@ventanamicro.com>

On Thu, Oct 12, 2023 at 10:45:05AM +0530, Anup Patel wrote:
> The frozen SBI v2.0 specification defines the SBI debug console
> (DBCN) extension which replaces the legacy SBI v0.1 console
> functions namely sbi_console_getchar() and sbi_console_putchar().
> 
> The SBI DBCN extension needs to be emulated in the KVM user-space
> (i.e. QEMU-KVM or KVMTOOL) so we forward SBI DBCN calls from KVM
> guest to the KVM user-space which can then redirect the console
> input/output to wherever it wants (e.g. telnet, file, stdio, etc).
> 
> The SBI debug console is simply a early console available to KVM
> guest for early prints and it does not intend to replace the proper
> console devices such as 8250, VirtIO console, etc.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  arch/riscv/include/asm/kvm_vcpu_sbi.h |  1 +
>  arch/riscv/include/uapi/asm/kvm.h     |  1 +
>  arch/riscv/kvm/vcpu_sbi.c             |  4 ++++
>  arch/riscv/kvm/vcpu_sbi_replace.c     | 32 +++++++++++++++++++++++++++
>  4 files changed, 38 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> index c02bda5559d7..6a453f7f8b56 100644
> --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h
> +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> @@ -73,6 +73,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi;
>  extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence;
>  extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_srst;
>  extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm;
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn;
>  extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental;
>  extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor;
>  
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 917d8cc2489e..60d3b21dead7 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -156,6 +156,7 @@ enum KVM_RISCV_SBI_EXT_ID {
>  	KVM_RISCV_SBI_EXT_PMU,
>  	KVM_RISCV_SBI_EXT_EXPERIMENTAL,
>  	KVM_RISCV_SBI_EXT_VENDOR,
> +	KVM_RISCV_SBI_EXT_DBCN,
>  	KVM_RISCV_SBI_EXT_MAX,
>  };
>  
> diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
> index 1b1cee86efda..bb76c3cf633f 100644
> --- a/arch/riscv/kvm/vcpu_sbi.c
> +++ b/arch/riscv/kvm/vcpu_sbi.c
> @@ -66,6 +66,10 @@ static const struct kvm_riscv_sbi_extension_entry sbi_ext[] = {
>  		.ext_idx = KVM_RISCV_SBI_EXT_PMU,
>  		.ext_ptr = &vcpu_sbi_ext_pmu,
>  	},
> +	{
> +		.ext_idx = KVM_RISCV_SBI_EXT_DBCN,
> +		.ext_ptr = &vcpu_sbi_ext_dbcn,
> +	},
>  	{
>  		.ext_idx = KVM_RISCV_SBI_EXT_EXPERIMENTAL,
>  		.ext_ptr = &vcpu_sbi_ext_experimental,
> diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c
> index 7c4d5d38a339..23b57c931b15 100644
> --- a/arch/riscv/kvm/vcpu_sbi_replace.c
> +++ b/arch/riscv/kvm/vcpu_sbi_replace.c
> @@ -175,3 +175,35 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_srst = {
>  	.extid_end = SBI_EXT_SRST,
>  	.handler = kvm_sbi_ext_srst_handler,
>  };
> +
> +static int kvm_sbi_ext_dbcn_handler(struct kvm_vcpu *vcpu,
> +				    struct kvm_run *run,
> +				    struct kvm_vcpu_sbi_return *retdata)
> +{
> +	struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
> +	unsigned long funcid = cp->a6;
> +
> +	switch (funcid) {
> +	case SBI_EXT_DBCN_CONSOLE_WRITE:
> +	case SBI_EXT_DBCN_CONSOLE_READ:
> +	case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
> +		/*
> +		 * The SBI debug console functions are unconditionally
> +		 * forwarded to the userspace.
> +		 */
> +		kvm_riscv_vcpu_sbi_forward(vcpu, run);
> +		retdata->uexit = true;
> +		break;
> +	default:
> +		retdata->err_val = SBI_ERR_NOT_SUPPORTED;
> +	}
> +
> +	return 0;
> +}
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn = {
> +	.extid_start = SBI_EXT_DBCN,
> +	.extid_end = SBI_EXT_DBCN,
> +	.default_unavail = true,
> +	.handler = kvm_sbi_ext_dbcn_handler,
> +};
> -- 
> 2.34.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

  reply	other threads:[~2023-10-19  8:02 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-12  5:15 [PATCH v2 0/8] RISC-V SBI debug console extension support Anup Patel
2023-10-12  5:15 ` [PATCH v2 1/8] RISC-V: Add defines for SBI debug console extension Anup Patel
2023-10-19  7:44   ` Andrew Jones
2023-10-12  5:15 ` [PATCH v2 2/8] RISC-V: KVM: Change the SBI specification version to v2.0 Anup Patel
2023-10-19  7:46   ` Andrew Jones
2023-10-12  5:15 ` [PATCH v2 3/8] RISC-V: KVM: Allow some SBI extensions to be disabled by default Anup Patel
2023-10-19  7:57   ` Andrew Jones
2023-10-20  5:26     ` Anup Patel
2023-10-12  5:15 ` [PATCH v2 4/8] RISC-V: KVM: Forward SBI DBCN extension to user-space Anup Patel
2023-10-19  8:01   ` Andrew Jones [this message]
2023-10-19  9:17   ` Andrew Jones
2023-10-12  5:15 ` [PATCH v2 5/8] RISC-V: Add inline version of sbi_console_putchar/getchar() functions Anup Patel
2023-10-19  8:03   ` Andrew Jones
2023-10-12  5:15 ` [PATCH v2 6/8] tty/serial: Add RISC-V SBI debug console based earlycon Anup Patel
2023-10-19  8:27   ` Andrew Jones
2023-10-12  5:15 ` [PATCH v2 7/8] tty: Add SBI debug console support to HVC SBI driver Anup Patel
2023-10-12 11:38   ` Björn Töpel
2023-10-13 15:41     ` Anup Patel
2023-10-12  5:15 ` [PATCH v2 8/8] RISC-V: Enable SBI based earlycon support Anup Patel
2023-10-19  8:46   ` Andrew Jones

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