From: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Valentin Schneider <vschneid@redhat.com>,
linux-kernel@vger.kernel.org, Nicholas Piggin <npiggin@gmail.com>,
Rohan McLure <rmclure@linux.ibm.com>,
linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
Josh Poimboeuf <jpoimboe@kernel.org>
Subject: Re: [PATCH v2 2/6] powerpc/smp: Enable Asym packing for cores on shared processor
Date: Thu, 19 Oct 2023 18:24:59 +0530 [thread overview]
Message-ID: <20231019125459.GG2194132@linux.vnet.ibm.com> (raw)
In-Reply-To: <20231019074828.GM33217@noisy.programming.kicks-ass.net>
* Peter Zijlstra <peterz@infradead.org> [2023-10-19 09:48:28]:
> On Thu, Oct 19, 2023 at 03:38:40PM +1100, Michael Ellerman wrote:
> > Srikar Dronamraju <srikar@linux.vnet.ibm.com> writes:
> > > If there are shared processor LPARs, underlying Hypervisor can have more
> > > virtual cores to handle than actual physical cores.
> > >
> > > Starting with Power 9, a core has 2 nearly independent thread groups.
> >
> > You need to be clearer here that you're talking about "big cores", not
> > SMT4 cores as seen on bare metal systems.
>
> What is a 'big core' ? I'm thinking big.LITTLE, but I didn't think Power
> went that route (yet?).. help?
>
Each independent thread group acts as a SMT4 core or a small core. A set of
2 thread groups form a SMT8 core aka big core. PowerVM aka pHYp schedules
at a big core granularity
So if we have 2 LPARS, each spanning 2 big cores, aka 16 CPUs, and if at
somepoint, each LPAR has only 2 threads to run, we are exploring if we can
run both the threads on just one big core, so that PhyP can schedule both
LPARS at the same time and avoid having to switch/multiplex between these
two LPARS.
--
Thanks and Regards
Srikar Dronamraju
next prev parent reply other threads:[~2023-10-19 12:56 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-18 16:37 [PATCH v2 0/6] powerpc/smp: Shared processor sched optimizations Srikar Dronamraju
2023-10-18 16:37 ` [PATCH v2 1/6] powerpc/smp: Cache CPU has Asymmetric SMP Srikar Dronamraju
2023-10-19 4:33 ` Michael Ellerman
2023-10-20 9:09 ` Srikar Dronamraju
2023-10-18 16:37 ` [PATCH v2 2/6] powerpc/smp: Enable Asym packing for cores on shared processor Srikar Dronamraju
2023-10-19 4:38 ` Michael Ellerman
2023-10-19 7:48 ` Peter Zijlstra
2023-10-19 11:50 ` Michael Ellerman
2023-10-19 12:54 ` Srikar Dronamraju [this message]
2023-10-19 15:56 ` Shrikanth Hegde
2023-10-20 5:44 ` Srikar Dronamraju
2023-10-18 16:37 ` [PATCH v2 3/6] powerpc/smp: Move shared_processor static key to smp.h Srikar Dronamraju
2023-10-19 4:41 ` Michael Ellerman
2023-10-19 13:08 ` Srikar Dronamraju
2023-10-20 10:44 ` Michael Ellerman
2023-10-19 10:30 ` Shrikanth Hegde
2023-10-18 16:37 ` [PATCH v2 4/6] powerpc/smp: Disable MC domain for shared processor Srikar Dronamraju
2023-10-19 4:48 ` Michael Ellerman
2023-10-19 7:50 ` Peter Zijlstra
2023-10-19 13:23 ` Srikar Dronamraju
2023-10-19 13:16 ` Srikar Dronamraju
2023-10-18 16:37 ` [PATCH v2 5/6] powerpc/smp: Add read_mostly attribute Srikar Dronamraju
2023-10-19 4:49 ` Michael Ellerman
2023-10-19 7:51 ` Peter Zijlstra
2023-10-19 12:56 ` Srikar Dronamraju
2023-10-18 16:37 ` [PATCH v2 6/6] powerpc/smp: Avoid asym packing within thread_group of a core Srikar Dronamraju
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