From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BC7ECDB47E for ; Fri, 20 Oct 2023 07:28:44 +0000 (UTC) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=iEdXYWFX; dkim-atps=neutral Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4SBbmV2CP5z3vsW for ; Fri, 20 Oct 2023 18:28:42 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=iEdXYWFX; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=ventanamicro.com (client-ip=2607:f8b0:4864:20::22f; helo=mail-oi1-x22f.google.com; envelope-from=apatel@ventanamicro.com; receiver=lists.ozlabs.org) Received: from mail-oi1-x22f.google.com (mail-oi1-x22f.google.com [IPv6:2607:f8b0:4864:20::22f]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4SBbdF0GWkz3dK7 for ; Fri, 20 Oct 2023 18:22:24 +1100 (AEDT) Received: by mail-oi1-x22f.google.com with SMTP id 5614622812f47-3b2df2fb611so393484b6e.0 for ; Fri, 20 Oct 2023 00:22:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697786542; x=1698391342; darn=lists.ozlabs.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y40VDpa5tFn1F2iuJCGX0eAdf56bF4H2v7CDU5J7JlM=; b=iEdXYWFXfUkwORDKCSi/DGxO1CjtYgMWmZu+m9c82l06tcrdwsPGcOQEzjZwu+sMUI nwh5uGpD1YlaRRWzZdsQagou3ahVDG21L7RqY6vE6s/adWxK2CoBFKUKUbWODJDQS7HE 7mMdDN1MXJ7ATXBN3lQyq2JGUkWDO2CGZ0VBZiY12JBOUJmMSnQpdD2CwB3vlx8HyUTN 5L/T7/vknsaHf/UUvG7WimLhSU+OTWZddCIOKFYNCeVnV73i6jpAAk0Ubcp2fyHUHk9p TvjQIubBYkrsZOIBSFdXh7kCjP72FyvUhgfFi36hIp6sG+xQzljF6U+hLch1bFmt4VP4 A9Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697786542; x=1698391342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y40VDpa5tFn1F2iuJCGX0eAdf56bF4H2v7CDU5J7JlM=; b=AazBEnpTEDAYqm1mg6i+kEEuCUEbR5XXKwGaFjvYCzwg1YlXU+tJrptfDJeIds8dke AyBA1SH3a78rzTcpoE2ah/7pBlzD1y9++O1D8yfV+JXeBDe9AG3MfCNMoP+OknuRMDU4 bSqMkxJsZ+9CJSz86n7OePcrb9cTK7r4gq86ZuJ3zIpX7xFiVPH710O9GPrCPQM9Vdiw 3Q+yBOP1HmkRySTP3eS5qhVfTK1GHUIPoD/LrD2Meiexon/IdbDeGoz6Y+vr4e7RADgh ayo0AiAikacr12S/iYicXnPS/HdtZ9E3M9PSaA1p/FcJfPVuc+wL4rpFLEFgSynkMHIq zmLQ== X-Gm-Message-State: AOJu0Yw9zQ/2jSP4qXXM1EOw1cgVtNl+DhtXv9V4tMM08o4t75fUrJxf guk6YmsmfRSxOUkRTHlLXFgN7w== X-Google-Smtp-Source: AGHT+IEUQYK4G0+aPnRjUR077ELz4RoscN7PlFXPrhd3l1/3Dp5w/UYmiQBCTNoQsdXF4g9TKR4q0g== X-Received: by 2002:a05:6808:55:b0:3af:d7dc:a47e with SMTP id v21-20020a056808005500b003afd7dca47emr1067018oic.42.1697786541699; Fri, 20 Oct 2023 00:22:21 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.83.81]) by smtp.gmail.com with ESMTPSA id v12-20020a63f20c000000b005b32d6b4f2fsm828204pgh.81.2023.10.20.00.22.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 00:22:21 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Subject: [PATCH v3 7/9] tty/serial: Add RISC-V SBI debug console based earlycon Date: Fri, 20 Oct 2023 12:51:38 +0530 Message-Id: <20231020072140.900967-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com> References: <20231020072140.900967-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , linux-serial@vger.kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Conor Dooley , kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Andrew Jones Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" We extend the existing RISC-V SBI earlycon support to use the new RISC-V SBI debug console extension. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/earlycon-riscv-sbi.c | 32 +++++++++++++++++++++---- 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index bdc568a4ab66..cec46091a716 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -87,7 +87,7 @@ config SERIAL_EARLYCON_SEMIHOST config SERIAL_EARLYCON_RISCV_SBI bool "Early console using RISC-V SBI" - depends on RISCV_SBI_V01 + depends on RISCV_SBI select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON diff --git a/drivers/tty/serial/earlycon-riscv-sbi.c b/drivers/tty/serial/earlycon-riscv-sbi.c index 27afb0b74ea7..c21cdef254e7 100644 --- a/drivers/tty/serial/earlycon-riscv-sbi.c +++ b/drivers/tty/serial/earlycon-riscv-sbi.c @@ -15,17 +15,41 @@ static void sbi_putc(struct uart_port *port, unsigned char c) sbi_console_putchar(c); } -static void sbi_console_write(struct console *con, - const char *s, unsigned n) +static void sbi_0_1_console_write(struct console *con, + const char *s, unsigned int n) { struct earlycon_device *dev = con->data; uart_console_write(&dev->port, s, n, sbi_putc); } +static void sbi_dbcn_console_write(struct console *con, + const char *s, unsigned int n) +{ + phys_addr_t pa = __pa(s); + + if (IS_ENABLED(CONFIG_32BIT)) + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + n, lower_32_bits(pa), upper_32_bits(pa), 0, 0, 0); + else + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + n, pa, 0, 0, 0, 0); +} + static int __init early_sbi_setup(struct earlycon_device *device, const char *opt) { - device->con->write = sbi_console_write; - return 0; + int ret = 0; + + if ((sbi_spec_version >= sbi_mk_version(2, 0)) && + (sbi_probe_extension(SBI_EXT_DBCN) > 0)) { + device->con->write = sbi_dbcn_console_write; + } else { + if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) + device->con->write = sbi_0_1_console_write; + else + ret = -ENODEV; + } + + return ret; } EARLYCON_DECLARE(sbi, early_sbi_setup); -- 2.34.1