From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B17BC004C0 for ; Sat, 21 Oct 2023 16:46:44 +0000 (UTC) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=EG2rxm/n; dkim-atps=neutral Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4SCS5v0Pldz3vX8 for ; Sun, 22 Oct 2023 03:46:43 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=EG2rxm/n; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linuxfoundation.org (client-ip=2604:1380:4601:e00::1; helo=ams.source.kernel.org; envelope-from=gregkh@linuxfoundation.org; receiver=lists.ozlabs.org) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4SCS4x0b2rz2yhT for ; Sun, 22 Oct 2023 03:45:52 +1100 (AEDT) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id CDC34B80E7B; Sat, 21 Oct 2023 16:45:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DA210C433C8; Sat, 21 Oct 2023 16:45:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1697906746; bh=MN1/oJukE4EkbtjF4EsDiPa4e+4k6rhpReY9dOx0rVo=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=EG2rxm/nXn3ve2cTPaP/raeMGmB70IeM1Ut27WsvANxOpR+Veq+GgHzIg+//lxz4d 6uLoJ0ZsctjIObzV1It7g+tCxrCAJLp6lzF65mWR7jFRpoYEsMeABM1F4q5uU5Dvok W1RsvxDiwmItNWuJHnqnamJDE9ZshM/EFWVQyZ1g= Date: Sat, 21 Oct 2023 18:45:43 +0200 From: Greg Kroah-Hartman To: Anup Patel Subject: Re: [PATCH v3 7/9] tty/serial: Add RISC-V SBI debug console based earlycon Message-ID: <2023102120-unleveled-composed-45a2@gregkh> References: <20231020072140.900967-1-apatel@ventanamicro.com> <20231020072140.900967-8-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231020072140.900967-8-apatel@ventanamicro.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-serial@vger.kernel.org, kvm@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Atish Patra , linux-kernel@vger.kernel.org, Conor Dooley , Palmer Dabbelt , kvm-riscv@lists.infradead.org, Paul Walmsley , Paolo Bonzini , linux-riscv@lists.infradead.org, Jiri Slaby , Andrew Jones Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Fri, Oct 20, 2023 at 12:51:38PM +0530, Anup Patel wrote: > We extend the existing RISC-V SBI earlycon support to use the new > RISC-V SBI debug console extension. > > Signed-off-by: Anup Patel > Reviewed-by: Andrew Jones > --- > drivers/tty/serial/Kconfig | 2 +- > drivers/tty/serial/earlycon-riscv-sbi.c | 32 +++++++++++++++++++++---- > 2 files changed, 29 insertions(+), 5 deletions(-) > > diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig > index bdc568a4ab66..cec46091a716 100644 > --- a/drivers/tty/serial/Kconfig > +++ b/drivers/tty/serial/Kconfig > @@ -87,7 +87,7 @@ config SERIAL_EARLYCON_SEMIHOST > > config SERIAL_EARLYCON_RISCV_SBI > bool "Early console using RISC-V SBI" > - depends on RISCV_SBI_V01 > + depends on RISCV_SBI > select SERIAL_CORE > select SERIAL_CORE_CONSOLE > select SERIAL_EARLYCON > diff --git a/drivers/tty/serial/earlycon-riscv-sbi.c b/drivers/tty/serial/earlycon-riscv-sbi.c > index 27afb0b74ea7..c21cdef254e7 100644 > --- a/drivers/tty/serial/earlycon-riscv-sbi.c > +++ b/drivers/tty/serial/earlycon-riscv-sbi.c > @@ -15,17 +15,41 @@ static void sbi_putc(struct uart_port *port, unsigned char c) > sbi_console_putchar(c); > } > > -static void sbi_console_write(struct console *con, > - const char *s, unsigned n) > +static void sbi_0_1_console_write(struct console *con, > + const char *s, unsigned int n) > { > struct earlycon_device *dev = con->data; > uart_console_write(&dev->port, s, n, sbi_putc); > } > > +static void sbi_dbcn_console_write(struct console *con, > + const char *s, unsigned int n) > +{ > + phys_addr_t pa = __pa(s); > + > + if (IS_ENABLED(CONFIG_32BIT)) > + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, > + n, lower_32_bits(pa), upper_32_bits(pa), 0, 0, 0); > + else > + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, > + n, pa, 0, 0, 0, 0); This is still a bit hard to follow, and I guarantee it will be a pain to maintain over time, trying to keep both calls in sync, right? Why not fix up sbi_ecall() to get this correct instead? It should be handling phys_addr_t values, not forcing you to do odd bit masking every single time you call it, right? That would make things much easier overall, and this patch simpler, as well as the next one. Oh wait, sbi_ecall() is crazy, and just a pass-through, so that's not going to work, you need a wrapper function for this mess to do that bit twiddeling for you instead of forcing you to do it each time, I guess that's what you are trying to do here, but ick, is it correct? thanks, greg k-h