From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C29BC004C0 for ; Sat, 21 Oct 2023 16:47:36 +0000 (UTC) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=jWi3ztDg; dkim-atps=neutral Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4SCS6t3xK1z3vXw for ; Sun, 22 Oct 2023 03:47:34 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=jWi3ztDg; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linuxfoundation.org (client-ip=145.40.68.75; helo=ams.source.kernel.org; envelope-from=gregkh@linuxfoundation.org; receiver=lists.ozlabs.org) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4SCS5Z2yqmz3vYk for ; Sun, 22 Oct 2023 03:46:26 +1100 (AEDT) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id 3D245B80EF5; Sat, 21 Oct 2023 16:46:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E9B7C433C7; Sat, 21 Oct 2023 16:46:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1697906782; bh=QA1JELgGP1CsBBp3+FEwheuuXUtC5NcVTyALFKgjWxs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=jWi3ztDgfd2In+Cpk7pjAzhuWb6ZKaeBrI7z2dT43VzEA+KWNpCKeBuH13HC6D1xN v4z+lbijsAF5WzYCOv3kZwvJuv5z3nMT40wExGeDPZT213BSk9cJjnG76st2LiltCA Qo/Lt6pgpi2+9muYtK8s2EAJ4Nfkr01oT948vwqc= Date: Sat, 21 Oct 2023 18:46:19 +0200 From: Greg Kroah-Hartman To: Anup Patel Subject: Re: [PATCH v3 8/9] tty: Add SBI debug console support to HVC SBI driver Message-ID: <2023102153-retread-narrow-54ee@gregkh> References: <20231020072140.900967-1-apatel@ventanamicro.com> <20231020072140.900967-9-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231020072140.900967-9-apatel@ventanamicro.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-serial@vger.kernel.org, kvm@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Atish Patra , Atish Patra , linux-kernel@vger.kernel.org, Conor Dooley , Palmer Dabbelt , kvm-riscv@lists.infradead.org, Paul Walmsley , Paolo Bonzini , linux-riscv@lists.infradead.org, Jiri Slaby , Andrew Jones Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Fri, Oct 20, 2023 at 12:51:39PM +0530, Anup Patel wrote: > From: Atish Patra > > RISC-V SBI specification supports advanced debug console > support via SBI DBCN extension. > > Extend the HVC SBI driver to support it. > > Signed-off-by: Atish Patra > Signed-off-by: Anup Patel > --- > drivers/tty/hvc/Kconfig | 2 +- > drivers/tty/hvc/hvc_riscv_sbi.c | 82 ++++++++++++++++++++++++++++++--- > 2 files changed, 76 insertions(+), 8 deletions(-) > > diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig > index 4f9264d005c0..6e05c5c7bca1 100644 > --- a/drivers/tty/hvc/Kconfig > +++ b/drivers/tty/hvc/Kconfig > @@ -108,7 +108,7 @@ config HVC_DCC_SERIALIZE_SMP > > config HVC_RISCV_SBI > bool "RISC-V SBI console support" > - depends on RISCV_SBI_V01 > + depends on RISCV_SBI > select HVC_DRIVER > help > This enables support for console output via RISC-V SBI calls, which > diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sbi.c > index 31f53fa77e4a..56da1a4b5aca 100644 > --- a/drivers/tty/hvc/hvc_riscv_sbi.c > +++ b/drivers/tty/hvc/hvc_riscv_sbi.c > @@ -39,21 +39,89 @@ static int hvc_sbi_tty_get(uint32_t vtermno, char *buf, int count) > return i; > } > > -static const struct hv_ops hvc_sbi_ops = { > +static const struct hv_ops hvc_sbi_v01_ops = { > .get_chars = hvc_sbi_tty_get, > .put_chars = hvc_sbi_tty_put, > }; > > -static int __init hvc_sbi_init(void) > +static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count) > { > - return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16)); > + phys_addr_t pa; > + struct sbiret ret; > + > + if (is_vmalloc_addr(buf)) { > + pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf); > + if (PAGE_SIZE < (offset_in_page(buf) + count)) > + count = PAGE_SIZE - offset_in_page(buf); > + } else { > + pa = __pa(buf); > + } > + > + if (IS_ENABLED(CONFIG_32BIT)) > + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, > + count, lower_32_bits(pa), upper_32_bits(pa), > + 0, 0, 0); > + else > + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, > + count, pa, 0, 0, 0, 0); Again, you need a helper function here to keep you from having to keep this all in sync. > + if (ret.error) > + return 0; > + > + return count; > } > -device_initcall(hvc_sbi_init); > > -static int __init hvc_sbi_console_init(void) > +static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count) > { > - hvc_instantiate(0, 0, &hvc_sbi_ops); > + phys_addr_t pa; > + struct sbiret ret; > + > + if (is_vmalloc_addr(buf)) { > + pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf); > + if (PAGE_SIZE < (offset_in_page(buf) + count)) > + count = PAGE_SIZE - offset_in_page(buf); > + } else { > + pa = __pa(buf); > + } > + > + if (IS_ENABLED(CONFIG_32BIT)) > + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, > + count, lower_32_bits(pa), upper_32_bits(pa), > + 0, 0, 0); > + else > + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, > + count, pa, 0, 0, 0, 0); And here too. thanks, greg k-h