From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70BE9C4167B for ; Thu, 30 Nov 2023 16:47:19 +0000 (UTC) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=fRxr8jo0; dkim-atps=neutral Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4Sh2D56S2Wz3dBt for ; Fri, 1 Dec 2023 03:47:17 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=fRxr8jo0; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linaro.org (client-ip=2607:f8b0:4864:20::f31; helo=mail-qv1-xf31.google.com; envelope-from=manivannan.sadhasivam@linaro.org; receiver=lists.ozlabs.org) Received: from mail-qv1-xf31.google.com (mail-qv1-xf31.google.com [IPv6:2607:f8b0:4864:20::f31]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4Sh2C72sPdz2ykC for ; Fri, 1 Dec 2023 03:46:27 +1100 (AEDT) Received: by mail-qv1-xf31.google.com with SMTP id 6a1803df08f44-67a295e40baso6561466d6.1 for ; Thu, 30 Nov 2023 08:46:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701362783; x=1701967583; darn=lists.ozlabs.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=kjHz7y8FdABfzePSYWvG3C7LR0AsyMP0bJ41uTORMXU=; b=fRxr8jo0uZo8xiGd7Yfe2k3/L4KeUlvcE6GM5QfWZMWFqbB1hzi4d6okIoS5ad8IcK rZAGY/x/zbae3Ivf0SlW/BQt4mz8B48lrIBSjd1H/151pFOSXkGMVJdzQWb+6wAbr0kf yqknS5Ojw2dViEnyWbvIaHcdWFZfxZgZRAfIGGxy6MiRd1lL9XksJBvrONOIdwImHyVC paJT2oWckjdXyOzmZthL7q+wgAjAKIaUpUGh+weyFdafNaY8b6tNQrwYm74AjYUmlRrK 0Rmi1NFFSemoEhYG5Yj7yUO2S0kGIbFYgwCj7+YgQgW+mdyiKmA1gAab3O5rSWUYOm1B 7GWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701362783; x=1701967583; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=kjHz7y8FdABfzePSYWvG3C7LR0AsyMP0bJ41uTORMXU=; b=HgBkdjEo4hqKhlq5bnu72bjIQT6BSgExwFi4KeHwA+W2bGDmsDcRujeW5LS52abx9+ B9ZqCql5uMU6NbckSdISB7WfWjDksgpkNeHOtxDxr0IgM1lD8RuT/L5//i929kf4JkTM kFSebe8rmeDfEQh/mBi3k8wp80xPOhPNhZuZdoFHcUsPznmjdVe1YQs8WQNWk9R4eQbe 98ruqJRzYBrnLP1B+XmqeGoeNu+4dZ20H/hgTccFcQUwPXAcPG29JZqDshUMgivOA1Yb nu1zHZM3YI1idab3rKojnlTIBGtGoYS6SU9nNU/edYFQDrl4voclCcufYa7p24gkQDoK L0fA== X-Gm-Message-State: AOJu0YyCFmFUtfdkQWx9tzxd9lSowLME/RDnEt+fWJMeT9c0561jyPSe e5eztXF/tzM8+PYlPluXFkfJ X-Google-Smtp-Source: AGHT+IGr+FYWyq9x/hJmkOaCYSyPqI1d2GXxR9QhDtHyNIh5/ut2psmnppxw1XpPHzUoptuB8eT7og== X-Received: by 2002:a05:6214:cce:b0:67a:1580:d7c3 with SMTP id 14-20020a0562140cce00b0067a1580d7c3mr35231818qvx.58.1701362783244; Thu, 30 Nov 2023 08:46:23 -0800 (PST) Received: from thinkpad ([117.213.102.92]) by smtp.gmail.com with ESMTPSA id h29-20020a0cab1d000000b0067a2a0b44ddsm650581qvb.44.2023.11.30.08.46.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 08:46:22 -0800 (PST) Date: Thu, 30 Nov 2023 22:16:12 +0530 From: Manivannan Sadhasivam To: Frank Li Subject: Re: [PATCH v4 3/4] PCI: layerscape: Rename pf_* as pf_lut_* Message-ID: <20231130164612.GU3043@thinkpad> References: <20231129214412.327633-1-Frank.Li@nxp.com> <20231129214412.327633-4-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20231129214412.327633-4-Frank.Li@nxp.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: imx@lists.linux.dev, kw@linux.com, linux-pci@vger.kernel.org, lpieralisi@kernel.org, linux-kernel@vger.kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, bhelgaas@google.com, linuxppc-dev@lists.ozlabs.org, robh@kernel.org, linux-arm-kernel@lists.infradead.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, Nov 29, 2023 at 04:44:11PM -0500, Frank Li wrote: > 'pf' and 'lut' is just difference name in difference chips, but basic it is > a MMIO base address plus an offset. > > Rename it to avoid duplicate pf_* and lut_* in driver. > > Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam Can you fix the name in pci-layerscape-ep.c also? - Mani > --- > > Notes: > pf_lut is better than pf_* or lut* because some chip use 'pf', some chip > use 'lut'. > > change from v1 to v4 > - new patch at v3 > > drivers/pci/controller/dwc/pci-layerscape.c | 34 ++++++++++----------- > 1 file changed, 17 insertions(+), 17 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c > index 42bca2c3b5c3e..590e07bb27002 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape.c > +++ b/drivers/pci/controller/dwc/pci-layerscape.c > @@ -44,7 +44,7 @@ > #define PCIE_IATU_NUM 6 > > struct ls_pcie_drvdata { > - const u32 pf_off; > + const u32 pf_lut_off; > const struct dw_pcie_host_ops *ops; > int (*exit_from_l2)(struct dw_pcie_rp *pp); > bool scfg_support; > @@ -54,13 +54,13 @@ struct ls_pcie_drvdata { > struct ls_pcie { > struct dw_pcie *pci; > const struct ls_pcie_drvdata *drvdata; > - void __iomem *pf_base; > + void __iomem *pf_lut_base; > struct regmap *scfg; > int index; > bool big_endian; > }; > > -#define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr) > +#define ls_pcie_pf_lut_readl_addr(addr) ls_pcie_pf_lut_readl(pcie, addr) > #define to_ls_pcie(x) dev_get_drvdata((x)->dev) > > static bool ls_pcie_is_bridge(struct ls_pcie *pcie) > @@ -101,20 +101,20 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) > iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); > } > > -static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off) > +static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off) > { > if (pcie->big_endian) > - return ioread32be(pcie->pf_base + off); > + return ioread32be(pcie->pf_lut_base + off); > > - return ioread32(pcie->pf_base + off); > + return ioread32(pcie->pf_lut_base + off); > } > > -static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) > +static void ls_pcie_pf_lut_writel(struct ls_pcie *pcie, u32 off, u32 val) > { > if (pcie->big_endian) > - iowrite32be(val, pcie->pf_base + off); > + iowrite32be(val, pcie->pf_lut_base + off); > else > - iowrite32(val, pcie->pf_base + off); > + iowrite32(val, pcie->pf_lut_base + off); > } > > static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > @@ -124,11 +124,11 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > u32 val; > int ret; > > - val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); > + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR); > val |= PF_MCR_PTOMR; > - ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); > + ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val); > > - ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, > + ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR, > val, !(val & PF_MCR_PTOMR), > PCIE_PME_TO_L2_TIMEOUT_US/10, > PCIE_PME_TO_L2_TIMEOUT_US); > @@ -147,15 +147,15 @@ static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) > * Set PF_MCR_EXL2S bit in LS_PCIE_PF_MCR register for the link > * to exit L2 state. > */ > - val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); > + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR); > val |= PF_MCR_EXL2S; > - ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); > + ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val); > > /* > * L2 exit timeout of 10ms is not defined in the specifications, > * it was chosen based on empirical observations. > */ > - ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, > + ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR, > val, !(val & PF_MCR_EXL2S), > 1000, > 10000); > @@ -243,7 +243,7 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { > }; > > static const struct ls_pcie_drvdata layerscape_drvdata = { > - .pf_off = 0xc0000, > + .pf_lut_off = 0xc0000, > .pm_support = true, > .exit_from_l2 = ls_pcie_exit_from_l2, > }; > @@ -293,7 +293,7 @@ static int ls_pcie_probe(struct platform_device *pdev) > > pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); > > - pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; > + pcie->pf_lut_base = pci->dbi_base + pcie->drvdata->pf_lut_off; > > if (pcie->drvdata->scfg_support) { > pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்