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Wed, 27 Aug 2025 19:26:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 20924C4CEF4; Wed, 27 Aug 2025 19:26:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756322781; bh=LsA7ZOxoBvYSNrrcpvDmb056rLUcRAIeEvgBLT/jOP8=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=mrMRCa8BgGthZWppKJVQhU2g5bmIIf9uvfJelrBiPml0sWYGWybHeNVkKKUMFTeWb 3jhF9XvQmLNoj81iZ7AysmkLVtmehHGU6s2CbtcFvsgPeo+KGQ5QPxKEZeTLqmI8AT w6/hWGAasWUszW3G85lzIdpn1NvTp4cn6CTm2aiouIZfuFou7iD3QgAEuy9tg2QLIE YU25hLJz7beNnwaaUo2mtLd6smZ7w9ysYG+w6P3O1Aachxs58HUCZ6lMDAFQeJmhL6 XmZTe30eLCnmsAJrTsg26IZID9NlOi7PZ9pUKbuL13S8JRzMH2Bew8CQl6vCxb+W8A NDPdu3rwJlQcw== Date: Wed, 27 Aug 2025 14:26:19 -0500 From: Bjorn Helgaas To: Lukas Wunner Cc: Ilpo Jarvinen , Sathyanarayanan Kuppuswamy , Mahesh J Salgaonkar , Oliver OHalloran , linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org Subject: Re: [PATCH] PCI/AER: Support errors introduced by PCIe r6.0 Message-ID: <20250827192619.GA896720@bhelgaas> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <21f1875b18d4078c99353378f37dcd6b994f6d4e.1756301211.git.lukas@wunner.de> On Wed, Aug 27, 2025 at 03:41:09PM +0200, Lukas Wunner wrote: > PCIe r6.0 defined five additional errors in the Uncorrectable Error > Status, Mask and Severity Registers (PCIe r7.0 sec 7.8.4.2ff). > > lspci has been supporting them since commit 144b0911cc0b ("ls-ecaps: > extend decode support for more fields for AER CE and UE status"): > > https://git.kernel.org/pub/scm/utils/pciutils/pciutils.git/commit/?id=144b0911cc0b > > Amend the AER driver to recognize them as well, instead of logging them as > "Unknown Error Bit". > > Signed-off-by: Lukas Wunner > Cc: stable@vger.kernel.org Applied to pci/aer for v6.18, thanks, Lukas! > --- > Last amendment of aer_uncorrectable_error_string[] was in 2019 for an > error introduced in PCIe r3.1, see commit 6458b438ebc1 ("PCI/AER: Add > PoisonTLPBlocked to Uncorrectable error counters"). > > drivers/pci/pcie/aer.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index e286c19..15ed541 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -43,7 +43,7 @@ > #define AER_ERROR_SOURCES_MAX 128 > > #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */ > -#define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/ > +#define AER_MAX_TYPEOF_UNCOR_ERRS 32 /* as per PCI_ERR_UNCOR_STATUS*/ > > struct aer_err_source { > u32 status; /* PCI_ERR_ROOT_STATUS */ > @@ -525,11 +525,11 @@ void pci_aer_exit(struct pci_dev *dev) > "AtomicOpBlocked", /* Bit Position 24 */ > "TLPBlockedErr", /* Bit Position 25 */ > "PoisonTLPBlocked", /* Bit Position 26 */ > - NULL, /* Bit Position 27 */ > - NULL, /* Bit Position 28 */ > - NULL, /* Bit Position 29 */ > - NULL, /* Bit Position 30 */ > - NULL, /* Bit Position 31 */ > + "DMWrReqBlocked", /* Bit Position 27 */ > + "IDECheck", /* Bit Position 28 */ > + "MisIDETLP", /* Bit Position 29 */ > + "PCRC_CHECK", /* Bit Position 30 */ > + "TLPXlatBlocked", /* Bit Position 31 */ > }; > > static const char *aer_agent_string[] = { > -- > 2.47.2 >