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Thu, 6 Nov 2025 18:25:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762453506; bh=IO6Ln6PxVJkvupdXH1DzGpt9VjwkaVOtfdDxUcDva38=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=ZXaCgMPHUTgCLcoPL1VLHH2zvP1kf6yjh44zuxcuMdBkdMCa8WghRBtj5MJrCqXBW IAQuQnbUD6UdMgzdBvqrQJauNmmEvn+5rD6qJlOiqnUuIA6UVpSlqCrgXmdxrHZXU5 rzXQUw4PzL3fhldQJmoBvY2AfKTfrduZ2a5iWHdzQyr2yQDPzrXgo2+pDTm+nIlaMB MbF+q2IixPQD/F6Xc+kEip6PmOBHTSF5aa3jTiOutj/RIP/5UkSWpbTqRVO0Xj+evJ 0VvMp/lgE2a3CDnE8Q8Cya8gAglUbWd6Ao4uLa6c7ZUcvo+VVZWdrSQ5HdlpcfSzDy Oac/hnAuWG2tw== Date: Thu, 6 Nov 2025 12:25:05 -0600 From: Bjorn Helgaas To: Hongxing Zhu Cc: Christian Zigotzky , Manivannan Sadhasivam , Bjorn Helgaas , "linux-pci@vger.kernel.org" , mad skateman , "R.T.Dickinson" , Christian Zigotzky , linuxppc-dev , "hypexed@yahoo.com.au" , Darren Stevens , "debian-powerpc@lists.debian.org" , John Paul Adrian Glaubitz , Lukas Wunner , "regressions@lists.linux.dev" , luigi burdo , Al , Roland Subject: Re: [PPC] Boot problems after the pci-v6.18-changes Message-ID: <20251106182505.GA1962607@bhelgaas> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Nov 06, 2025 at 08:48:16AM +0000, Hongxing Zhu wrote: > ... > I tested these patches on i.MX95 EVK board with NVME storage device. > Because that i.MX95 PCIe RC failed enter into L2 when one NVME > device is connected to the port if ASPM L1 is enabled in default. > > These patches work as expected, the l0s and l1 can be disabled after > adding the following quirk. > > "DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PHILIPS, PCI_ANY_ID, > quirk_disable_aspm_l0s_l1_cap);" Thanks for trying this out. So if I understand correctly, the i.MX95 Root Port has PCI_VENDOR_ID_PHILIPS, and if ASPM L1 is enabled on its link, the link doesn't go to L2 when suspending? But it *does* go to L2 on suspend if L1 is disabled? I wonder if the issue is with the RC or with the NVMe device. The comments in dw_pcie_suspend_noirq() and qcom_pcie_suspend_noirq() make me wonder if there's something weird about NVMe and L2. I assume you don't want to disable L0s and L1 for *all* devices with PCI_VENDOR_ID_PHILIPS though. Aren't there endpoints with that ID that can use L0s and L1? And I suppose the best thing would be if we could enable L0s and L1, but turn them off before suspending? That would require something different, like something in imx_pcie_suspend_noirq() or a DECLARE_PCI_FIXUP_SUSPEND() quirk.