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T . Dickinson" , Darren Stevens , John Paul Adrian Glaubitz , Lukas Wunner , luigi burdo , Al , Roland , Hongxing Zhu , hypexed@yahoo.com.au, linuxppc-dev@lists.ozlabs.org, debian-powerpc@lists.debian.org, linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: [PATCH 0/2] PCI/ASPM: Allow quirks to avoid L0s and L1 Date: Thu, 6 Nov 2025 12:36:37 -0600 Message-ID: <20251106183643.1963801-1-helgaas@kernel.org> X-Mailer: git-send-email 2.43.0 X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Bjorn Helgaas We enabled ASPM too aggressively in v6.18-rc1. f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms") enabled ASPM L0s, L1, and (if advertised) L1 PM Substates. L1 PM Substates and Clock PM in particular are a problem because they depend on CLKREQ# and sometimes device-specific configuration, and none of this is discoverable in a generic way. df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for devicetree platforms") (v6.18-rc3) backed off and omitted Clock PM and L1 Substates. L0s and L1 are generically discoverable, but some devices advertise them even though they don't work correctly. This series is a way to avoid L0s and L1 in that case. Bjorn Helgaas (2): PCI/ASPM: Cache Link Capabilities so quirks can override them PCI/ASPM: Avoid L0s and L1 on Freescale Root Ports drivers/pci/pcie/aspm.c | 42 ++++++++++++++++++++--------------------- drivers/pci/probe.c | 5 ++--- drivers/pci/quirks.c | 12 ++++++++++++ include/linux/pci.h | 1 + 4 files changed, 36 insertions(+), 24 deletions(-) -- 2.43.0