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From: Bjorn Helgaas <helgaas@kernel.org>
To: Shuai Xue <xueshuai@linux.alibaba.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linuxppc-dev@lists.ozlabs.org, bhelgaas@google.com,
	kbusch@kernel.org, sathyanarayanan.kuppuswamy@linux.intel.com,
	lukas@wunner.de, mahesh@linux.ibm.com, oohall@gmail.com,
	Jonathan.Cameron@huawei.com, terry.bowman@amd.com,
	tianruidong@linux.alibaba.com, zhuo.song@linux.alibaba.com,
	oliver.yang@linux.alibaba.com
Subject: Re: [PATCH v3] PCI/AER: Only clear error bits in PCIe Device Status register
Date: Thu, 12 Feb 2026 15:18:34 -0600	[thread overview]
Message-ID: <20260212211834.GA3075092@bhelgaas> (raw)
In-Reply-To: <20260211124624.49656-1-xueshuai@linux.alibaba.com>

On Wed, Feb 11, 2026 at 08:46:24PM +0800, Shuai Xue wrote:
> Currently, pcie_clear_device_status() clears the entire PCIe Device
> Status register (PCI_EXP_DEVSTA) by writing back the value read from
> the register, which affects not only the error status bits but also
> other writable bits.
> 
> According to PCIe Base Specification r7.0, sec 7.5.3.5 (Device Status
> Register), this register contains:
> 
> - RW1C error status bits (CED, NFED, FED, URD at bits 0-3): These are
>   the four error status bits that need to be cleared.
> 
> - Read-only bits (AUXPD at bit 4, TRPND at bit 5): Writing to these
>   has no effect.
> 
> - Emergency Power Reduction Detected (bit 6): A RW1C non-error bit
>   introduced in PCIe r5.0 (2019). This is currently the only writable
>   non-error bit in the Device Status register. Unconditionally
>   clearing this bit can interfere with other software components that
>   rely on this power management indication.
> 
> - Reserved bits (RsvdZ): These bits are required to be written as
>   zero. Writing 1s to them (as the current implementation may do)
>   violates the specification.
> 
> To prevent unintended side effects, modify pcie_clear_device_status()
> to only write 1s to the four error status bits (CED, NFED, FED, URD),
> leaving the Emergency Power Reduction Detected bit and reserved bits
> unaffected.
> 
> Fixes: ec752f5d54d7 ("PCI/AER: Clear device status bits during ERR_FATAL and ERR_NONFATAL")
> Cc: stable@vger.kernel.org
> Suggested-by: Lukas Wunner <lukas@wunner.de>
> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> Reviewed-by: Lukas Wunner <lukas@wunner.de>
> Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>

Applied to pci/aer for v7.1, thank you!

This branch will be rebased to v7.0-rc1 when it is tagged.

> ---
> changes since v2:
> - accommodate two macros per line per Lukas
> - pick up Reviewed-by tag from Lukas
> ---
>  drivers/pci/pci.c | 7 +++----
>  1 file changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 13dbb405dc31..0e6a50260555 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -2243,10 +2243,9 @@ EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
>  #ifdef CONFIG_PCIEAER
>  void pcie_clear_device_status(struct pci_dev *dev)
>  {
> -	u16 sta;
> -
> -	pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
> -	pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
> +	pcie_capability_write_word(dev, PCI_EXP_DEVSTA,
> +				   PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
> +				   PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD);
>  }
>  #endif
>  
> -- 
> 2.43.5
> 


      reply	other threads:[~2026-02-12 21:18 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-11 12:46 [PATCH v3] PCI/AER: Only clear error bits in PCIe Device Status register Shuai Xue
2026-02-12 21:18 ` Bjorn Helgaas [this message]

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