[PATCH v4 3/3] ASoC: fsl_xcvr: add bitcount and timestamp controls

Shengjiu Wang
2026-03-06T09:39:14Z

The transmitter and receiver implement separate timestamp counters and
bit counters. The bit counter increments at the end of each bit in a
frame whenever the transmitter or receiver is enabled. The bit counter
can be reset by software. The timestamp counter increments on the bus
interface clock whenever it is enabled. The current value of the
timestamp counter is latched whenever the bit counter increments.
Reading the bit counter register will cause the latched timestamp
value to be saved in the bit counter timestamp register. The timestamp
counter can be reset by software, this also resets the latched timestamp
value and the bit counter timestamp register.

The timestamp counter and bit counter can be used by software to track
the progress of the transmitter and receiver. It can also be used to
calculate the relative frequency of the bit clock against the bus
interface clock.

As there are three regmap handlers defined in this driver, explicitly
call the snd_soc_component_init_regmap() to init regmap handler for the
component.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
sound/soc/fsl/fsl_xcvr.c | 64 ++++++++++++++++++++++++++++++++++++++++
sound/soc/fsl/fsl_xcvr.h | 18 +++++++++++
2 files changed, 82 insertions(+)

diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
index a268fb81a2f8..a945defa8b3f 100644
--- a/sound/soc/fsl/fsl_xcvr.c
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -62,6 +62,58 @@ struct fsl_xcvr {
u32 spdif_constr_rates_list[SPDIF_NUM_RATES];
};

+static const char * const inc_mode[] = {
+ "On enabled and bitcount increment", "On enabled"
+};
+
+static SOC_ENUM_SINGLE_DECL(transmit_tstmp_enum,
+ FSL_XCVR_TX_DPTH_CNTR_CTRL,
+ FSL_XCVR_TX_DPTH_CNTR_CTRL_TSINC_SHIFT, inc_mode);
+static SOC_ENUM_SINGLE_DECL(receive_tstmp_enum,
+ FSL_XCVR_RX_DPTH_CNTR_CTRL,
+ FSL_XCVR_RX_DPTH_CNTR_CTRL_TSINC_SHIFT, inc_mode);
+
+static const struct snd_kcontrol_new fsl_xcvr_timestamp_ctrls[] = {
+ SOC_SINGLE_EXT("Transmit Timestamp Control Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL,
+ FSL_XCVR_TX_DPTH_CNTR_CTRL_TSEN_SHIFT, 1, 0,
+ fsl_asoc_get_volsw, fsl_asoc_put_volsw),
+ SOC_ENUM_EXT("Transmit Timestamp Increment", transmit_tstmp_enum,
+ fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
+ SOC_SINGLE_EXT("Transmit Timestamp Reset", FSL_XCVR_TX_DPTH_CNTR_CTRL,
+ FSL_XCVR_TX_DPTH_CNTR_CTRL_RTSC_SHIFT, 1, 0,
+ fsl_asoc_get_volsw, fsl_asoc_put_volsw),
+ SOC_SINGLE_EXT("Transmit Bit Counter Reset", FSL_XCVR_TX_DPTH_CNTR_CTRL,
+ FSL_XCVR_TX_DPTH_CNTR_CTRL_RBC_SHIFT, 1, 0,
+ fsl_asoc_get_volsw, fsl_asoc_put_volsw),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Timestamp Counter", FSL_XCVR_TX_DPTH_TSCR,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Counter", FSL_XCVR_TX_DPTH_BCR,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Count Timestamp", FSL_XCVR_TX_DPTH_BCTR,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Latched Timestamp Counter", FSL_XCVR_TX_DPTH_BCRR,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+ SOC_SINGLE_EXT("Receive Timestamp Control Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL,
+ FSL_XCVR_RX_DPTH_CNTR_CTRL_TSEN_SHIFT, 1, 0,
+ fsl_asoc_get_volsw, fsl_asoc_put_volsw),
+ SOC_ENUM_EXT("Receive Timestamp Increment", receive_tstmp_enum,
+ fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
+ SOC_SINGLE_EXT("Receive Timestamp Reset", FSL_XCVR_RX_DPTH_CNTR_CTRL,
+ FSL_XCVR_RX_DPTH_CNTR_CTRL_RTSC_SHIFT, 1, 0,
+ fsl_asoc_get_volsw, fsl_asoc_put_volsw),
+ SOC_SINGLE_EXT("Receive Bit Counter Reset", FSL_XCVR_RX_DPTH_CNTR_CTRL,
+ FSL_XCVR_RX_DPTH_CNTR_CTRL_RBC_SHIFT, 1, 0,
+ fsl_asoc_get_volsw, fsl_asoc_put_volsw),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Timestamp Counter", FSL_XCVR_RX_DPTH_TSCR,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Counter", FSL_XCVR_RX_DPTH_BCR,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Count Timestamp", FSL_XCVR_RX_DPTH_BCTR,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Latched Timestamp Counter", FSL_XCVR_RX_DPTH_BCRR,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+};
+
static const struct fsl_xcvr_pll_conf {
u8 mfi; /* min=0x18, max=0x38 */
u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */
@@ -1070,8 +1122,20 @@ static struct snd_soc_dai_driver fsl_xcvr_dai = {
},
};

+static int fsl_xcvr_component_probe(struct snd_soc_component *component)
+{
+ struct fsl_xcvr *xcvr = snd_soc_component_get_drvdata(component);
+
+ snd_soc_component_init_regmap(component, xcvr->regmap);
+
+ return 0;
+}
+
static const struct snd_soc_component_driver fsl_xcvr_comp = {
.name = "fsl-xcvr-dai",
+ .probe = fsl_xcvr_component_probe,
+ .controls = fsl_xcvr_timestamp_ctrls,
+ .num_controls = ARRAY_SIZE(fsl_xcvr_timestamp_ctrls),
.legacy_dai_naming = 1,
};

diff --git a/sound/soc/fsl/fsl_xcvr.h b/sound/soc/fsl/fsl_xcvr.h
index dade3945cc0c..0cc7945b1d9f 100644
--- a/sound/soc/fsl/fsl_xcvr.h
+++ b/sound/soc/fsl/fsl_xcvr.h
@@ -233,6 +233,24 @@
#define FSL_XCVR_TX_DPTH_CTRL_CLK_RATIO BIT(29)
#define FSL_XCVR_TX_DPTH_CTRL_TM_NO_PRE_BME GENMASK(31, 30)

+#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TSEN_SHIFT 0
+#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TSEN BIT(0)
+#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TSINC_SHIFT 1
+#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TSINC BIT(1)
+#define FSL_XCVR_RX_DPTH_CNTR_CTRL_RBC_SHIFT 8
+#define FSL_XCVR_RX_DPTH_CNTR_CTRL_RBC BIT(8)
+#define FSL_XCVR_RX_DPTH_CNTR_CTRL_RTSC_SHIFT 9
+#define FSL_XCVR_RX_DPTH_CNTR_CTRL_RTSC BIT(9)
+
+#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TSEN_SHIFT 0
+#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TSEN BIT(0)
+#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TSINC_SHIFT 1
+#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TSINC BIT(1)
+#define FSL_XCVR_TX_DPTH_CNTR_CTRL_RBC_SHIFT 8
+#define FSL_XCVR_TX_DPTH_CNTR_CTRL_RBC BIT(8)
+#define FSL_XCVR_TX_DPTH_CNTR_CTRL_RTSC_SHIFT 9
+#define FSL_XCVR_TX_DPTH_CNTR_CTRL_RTSC BIT(9)
+
#define FSL_XCVR_PHY_AI_CTRL_AI_RESETN BIT(15)
#define FSL_XCVR_PHY_AI_CTRL_AI_RWB BIT(31)

--
2.34.1