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Tue, 21 Apr 2026 15:07:02 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay07.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 63LF6whG46072118 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 21 Apr 2026 15:06:58 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B99A320040; Tue, 21 Apr 2026 15:06:58 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 12CB920043; Tue, 21 Apr 2026 15:06:57 +0000 (GMT) Received: from Mac.ibm.com (unknown [9.39.27.248]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 21 Apr 2026 15:06:56 +0000 (GMT) From: Shivani Nittor To: maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org Cc: atrajeev@linux.ibm.com, hbathini@linux.vnet.ibm.com, Tejas.Manhas1@ibm.com, shivani@linux.ibm.com Subject: [PATCH] powerpc/perf: Update check for PERF_SAMPLE_DATA_SRC marked events Date: Tue, 21 Apr 2026 20:36:28 +0530 Message-ID: <20260421150628.96500-1-shivani@linux.ibm.com> X-Mailer: git-send-email 2.50.1 X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Vi3li3NtRY9_eEiJx2sIwqrC4EBW0O7h X-Proofpoint-ORIG-GUID: Vi3li3NtRY9_eEiJx2sIwqrC4EBW0O7h X-Authority-Analysis: v=2.4 cv=VP7tWdPX c=1 sm=1 tr=0 ts=69e79297 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=Ekv465IJch5wPuehOcwA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIxMDE0OCBTYWx0ZWRfX9q561O1116Jw uaNRtiPaeMEs1+2o+/drOeKD3p0k/OFuI62/nH/huhw5eNHwdjWt+lqaOy1gHkAXJ5T8lwkhSvA dC+x8BD11TrNHnWPfauyEIP2yJx5t6/LiFTdZ3KUQThU/CaY3eYHgis72ehOoTN6gjWgM7usASX urzV86ki4OBripfDQhXcGiuHfGo9jQPAiD2UTDMra5TuHUPCrWp/9iuQMnojzEuOsZJMj7jVLBG VGHEspAKUWntdPP8CqYXXTfjiUHIOR2u0sot0LW3Ptx993gcwbeLQ0b+7EuB8f2iHQcCL47Zzkk NNXFfPLH3H+/dwUWLkoA7KHeU53BxLK0ZWu4VOJszrJLmG946FpjPMSJMuLqeN9oc3Kz+2Fb6zs KBHmYCMWJIjILjGCqQUaAuu7v8FInlUmg6/iFMJzLHjbY0OgMYv2xm4NlMMQceQfs2usgBvqtzL ikm9tL5ZZ1VNa18sGdQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-21_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 impostorscore=0 suspectscore=0 priorityscore=1501 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210148 The core-book3s PMU sampling code validates the SIER TYPE field when PERF_SAMPLE_DATA_SRC is requested. The SIER TYPE field indicates the instruction type and is only valid for random sampling (marked events). To handle cases observed where SIER TYPE could be zero even for marked events,validation was added to drop such samples and increment event->lost_samples. However, this validation was applied to all samples, including continuous sampling. In continuous sampling mode, the PMU does not set the SIER TYPE field, so it remains zero. As a result, valid continuous samples were incorrectly treated as invalid and dropped. Fixed this by gating the SIER TYPE validation with mark_event, so the check runs only for marked (random) events. Continuous samples now skip this check and are recorded normally in the final data recording path. Fixes: 2ffb26afa642 ("arch/powerpc/perf: Check the instruction type before creating sample with perf_mem_data_src") Signed-off-by: Shivani Nittor --- arch/powerpc/perf/core-book3s.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 8b0081441f85..2e6adf5b95c4 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -2242,6 +2242,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val, const u64 last_period = event->hw.last_period; s64 prev, delta, left; int record = 0; + int mark_event = regs->dsisr & MMCRA_SAMPLE_ENABLE; if (event->hw.state & PERF_HES_STOPPED) { write_pmc(event->hw.idx, 0); @@ -2304,9 +2305,9 @@ static void record_and_restart(struct perf_event *event, unsigned long val, * In ISA v3.0 and before values "0" and "7" are considered reserved. * In ISA v3.1, value "7" has been used to indicate "larx/stcx". * Drop the sample if "type" has reserved values for this field with a - * ISA version check. + * ISA version check for marked events. */ - if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && + if (mark_event && event->attr.sample_type & PERF_SAMPLE_DATA_SRC && ppmu->get_mem_data_src) { val = (regs->dar & SIER_TYPE_MASK) >> SIER_TYPE_SHIFT; if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31))) { -- 2.47.3