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Thu, 16 Jul 2026 07:52:52 -0700 (PDT) Received: from ziepe.ca ([159.2.72.92]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51ec9fef211sm28849141cf.0.2026.07.16.07.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2026 07:52:51 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1wkNSF-00000002ZDm-0DPq; Thu, 16 Jul 2026 11:52:51 -0300 Date: Thu, 16 Jul 2026 11:52:51 -0300 From: Jason Gunthorpe To: Alexey Kardashevskiy Cc: "Aneesh Kumar K.V" , Catalin Marinas , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, Robin Murphy , Marek Szyprowski , Will Deacon , Marc Zyngier , Steven Price , Suzuki K Poulose , Jiri Pirko , Mostafa Saleh , Petr Tesarik , Dan Williams , Xu Yilun , linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Alexander Gordeev , Gerald Schaefer , Heiko Carstens , Vasily Gorbik , Christian Borntraeger , Sven Schnelle , x86@kernel.org, Jiri Pirko , Michael Kelley Subject: Re: [PATCH v7 16/22] dma-direct: make dma_direct_map_phys() honor DMA_ATTR_CC_SHARED Message-ID: <20260716145251.GE210048@ziepe.ca> References: <20260701054926.825925-1-aneesh.kumar@kernel.org> <20260701054926.825925-17-aneesh.kumar@kernel.org> <9d83ec13-3b1e-4c1b-8bab-16ea057cfba0@amd.com> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9d83ec13-3b1e-4c1b-8bab-16ea057cfba0@amd.com> On Thu, Jul 16, 2026 at 11:55:20AM +1000, Alexey Kardashevskiy wrote: > > > For AMD/SME, on host with memory encryption we now end up setting the C > > > bit for DMA_ATTR_MMIO. This is fine for RAM but not sure whether > > > some other MMIO bus understands this attribute. Maybe we should stick to > > > something like __phys_to_dma() for the !CC_SHARED && MMIO path. Or, > > > since this is not universally defined, just use the old dma_addr = phys > > > if MMIO and ignore any unlikely DMA offsets. > > > > > > > Considering for AMD/SME system an unencrypted dma addr is one without C > > bit, will this be good? > > Normally both encrypted and unencrypted DMA addresses do not have > Cbit, with the only exception of "iommu=pt" (which is not the > default afaik). And in this case, having Cbit in DMA handles only > makes sense if p2p trafic goes via the root port (== IOMMU in > passthrough mode, and I am not sure even about if the root port will > convert this Cbit to T=1 MMIO in this mode) but if it goes via some > PCI bridge - then Cbit won't mean encryption for sure. But I do not > know much about p2p (never touched). But in any case > force_dma_unencrypted() seems to make no sense here. True p2p through a switch does not call the DMA API at all, it directly stuffs the physical MMIO BAR address of the target into the dma_addr_t - which won't have a C bit. The DMA API is only involved if the p2p will transit through the root port, so adding the C bit is correct. AFAICT it is iommu=!pt that doesn't work at all since the AMD IOMMU driver always does __sme_set() even for MMIO when forming the IOPTE, which I guess is wrong for MMIO. Jason