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Wed, 23 Sep 2026 11:40:30 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e34]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cc75f3b82aasm1644341a12.9.2026.09.23.11.40.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 11:40:29 -0700 (PDT) From: Rosen Penev To: linuxppc-dev@lists.ozlabs.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , "Ritesh Harjani (IBM)" , Shrikanth Hegde , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH] powerpc: dts: turris1x: use qca8337 internal PHYs Date: Wed, 23 Sep 2026 11:40:28 -0700 Message-ID: <20260923184028.13830-1-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The QCA8337 switch has a managed internal MDIO bus for its built-in PHYs. Declare the five PHYs in an mdio subnode of the switch and link the LAN ports to them with phy-mode = "internal" and phy-handle, so each switch port is connected to the correct internal PHY instead of relying on the implicit legacy port-to-PHY mapping. Assisted-by: LLM Signed-off-by: Rosen Penev --- arch/powerpc/boot/dts/turris1x.dts | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/powerpc/boot/dts/turris1x.dts b/arch/powerpc/boot/dts/turris1x.dts index d0b7c62b8c6e..58c9e7b34e50 100644 --- a/arch/powerpc/boot/dts/turris1x.dts +++ b/arch/powerpc/boot/dts/turris1x.dts @@ -174,26 +174,36 @@ fixed-link { port@1 { reg = <1>; label = "lan5"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; }; port@2 { reg = <2>; label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; }; port@3 { reg = <3>; label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; }; port@4 { reg = <4>; label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; }; port@5 { reg = <5>; label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; }; port@6 { @@ -208,6 +218,31 @@ fixed-link { }; }; }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: ethernet-phy@0 { + reg = <0>; + }; + + phy_port2: ethernet-phy@1 { + reg = <1>; + }; + + phy_port3: ethernet-phy@2 { + reg = <2>; + }; + + phy_port4: ethernet-phy@3 { + reg = <3>; + }; + + phy_port5: ethernet-phy@4 { + reg = <4>; + }; + }; }; }; -- 2.55.0