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bh=44zkx5wXiPoFVTiEc5KY1Ag9ipCGGabDIfpXco19T3Q=; b=jCzk9hTbee0XNR63+11ejFjl4fKqlhgUpFIB+49LEQdLQOndENOkjl1QeeT9kwQBk8 g4FoK8+9sp/3yOFIae8QdpONad5msEuIieoA5q2uXwOoZFBGGwm7T21cuB34iu6RHsZS ttC7ZrNin2Pb9ccRS8pv8jcemwVyI+kqfaOaSJ7OAgFXEoXEwVFfqdiJGjZwM9mumFmP I0AS2hXQgw1gn5cYyCG+WoJ5YW/e5JrIWTV6w09swMv0S5w3JRvldCwh3aa6UwA2Vxcs 5RHTaCqxUQiBY3IsjBKuEChFJnB/fUX9nU9RPfOBBlPU4fLLH26gayLD5TI1//IUHVcY zkSw== X-Forwarded-Encrypted: i=1; AKwUvBxE/HKC/nE8MfZ5VzbzcZDhH7xH1sKtraie5hA4sMhK4++hLOOiW9PpuLEJzfO4qyTZbIaT7S4lf0X7bvE=@lists.ozlabs.org X-Gm-Message-State: AFuF++lAIT8EtHC3aiI0P88MHi0zUsn0ZKiPBUdFzaUioRWD4GEXmlbe nqcaeptXvvegXlP06UEDcPwIW/mFs8zzcfL0s5Cv3KiLxPlXNSNhtaYRky4XY0rmsZ4E3hgpvP/ LzOp1IUDlgo81Yw== X-Received: from pgbfq21.prod.google.com ([2002:a05:6a02:2995:b0:c88:e5cb:265]) (user=dmatlack job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:3d09:b0:3dd:a196:906f with SMTP id adf61e73a8af0-3de0e942ae3mr2935846637.57.1790271312798; Thu, 24 Sep 2026 10:35:12 -0700 (PDT) Date: Thu, 24 Sep 2026 17:34:52 +0000 In-Reply-To: <20260924173501.856380-1-dmatlack@google.com> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list Mime-Version: 1.0 References: <20260924173501.856380-1-dmatlack@google.com> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20260924173501.856380-7-dmatlack@google.com> Subject: [PATCH 06/15] PCI/ASPM: Save LTR state in the saved capability store From: David Matlack To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Cc: Alex Williamson , Bjorn Helgaas , Jason Gunthorpe , Josh Hilke , Lukas Wunner , Mahesh J Salgaonkar , "Oliver O'Halloran" , Pasha Tatashin , Pratyush Yadav , Samiullah Khawaja , Vipin Sharma , David Matlack Content-Type: text/plain; charset="UTF-8" Save and restore the LTR maximum latency registers through the per-device saved capability store instead of a private pci_cap_saved_state buffer. Reserve the DWORD by its configuration space offset during device setup, and keep accessing the registers a DWORD at a time because some devices only support DWORD access to them. No functional change intended. Assisted-by: LLM Signed-off-by: David Matlack --- drivers/pci/pci.c | 12 ++++++++---- drivers/pci/pcie/aspm.c | 19 +++---------------- 2 files changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 9e49806c6891..e53bca1cb50f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3580,10 +3580,14 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev) pci_err(dev, "unable to reserve PCI-X save state\n"); } - error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR, - 2 * sizeof(u16)); - if (error) - pci_err(dev, "unable to allocate suspend buffer for LTR\n"); + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); + if (pos) { + unsigned int off = pos + PCI_LTR_MAX_SNOOP_LAT; + + error = pci_reserve_saved_cap(dev, off, sizeof(u32)); + if (error) + pci_err(dev, "unable to reserve LTR save state\n"); + } pci_allocate_vc_save_buffers(dev); } diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 02922b887ec6..16f22af98686 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -30,8 +30,6 @@ void pci_save_ltr_state(struct pci_dev *dev) { int ltr; - struct pci_cap_saved_state *save_state; - u32 *cap; if (!pci_is_pcie(dev)) return; @@ -40,31 +38,20 @@ void pci_save_ltr_state(struct pci_dev *dev) if (!ltr) return; - save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); - if (!save_state) { - pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n"); - return; - } - /* Some broken devices only support dword access to LTR */ - cap = &save_state->cap.data[0]; - pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap); + pci_save_cap_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT); } void pci_restore_ltr_state(struct pci_dev *dev) { - struct pci_cap_saved_state *save_state; int ltr; - u32 *cap; - save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); - if (!save_state || !ltr) + if (!ltr) return; /* Some broken devices only support dword access to LTR */ - cap = &save_state->cap.data[0]; - pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap); + pci_restore_cap_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT); } void pci_configure_aspm_l1ss(struct pci_dev *pdev) -- 2.56.0.rc1.315.gc6ed9934b7-goog