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(unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wD3Dz_umOBqUsqlCw--.64541S5; Tue, 27 Oct 2026 20:28:34 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v4 03/16] PCI: dwc: imx6: Use cached PCIe capability offset Date: Tue, 27 Oct 2026 20:28:14 +0800 Message-ID: <20261027122827.2725643-4-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261027122827.2725643-1-18255117159@163.com> References: <20261027122827.2725643-1-18255117159@163.com> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , Precedence: list X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:_____wD3Dz_umOBqUsqlCw--.64541S5 X-Coremail-Antispam: 1Uf129KBjvJXoW7uFyruw4UKr1UtFWxKw1xKrg_yoW8Ww4Upa 9xurWFyF4rJF4SvFs2ya15uF13tas0kr4UJan3Kw1avFy7t34UWFy0kryftF43Kr4vgry2 yF17t3WxG39ayF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziBT5dUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6xI12GrgmPIXkwAA3w X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, FROM_LOCAL_DIGITS,FROM_LOCAL_HEX,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Replace the two dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) calls in imx_pcie_ltssm_enable() and imx_pcie_start_link() with dw_pcie_get_pcie_cap(). Both functions run with the controller powered and clocked: they are reached either from the host .start_link callback or, in Endpoint mode, after the PERST# deassert path has enabled the resources. The helper therefore performs the DBI read at the same point as the replaced call and caches the result for later invocations, which is useful for suspend/resume where the link is started again. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pci-imx6.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 39790e66b98d..7fe9c1fa2686 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -970,7 +970,7 @@ static void imx_pcie_ltssm_enable(struct device *dev) { struct imx_pcie *imx_pcie = dev_get_drvdata(dev); const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; - u8 offset = dw_pcie_find_capability(imx_pcie->pci, PCI_CAP_ID_EXP); + u8 offset = dw_pcie_get_pcie_cap(imx_pcie->pci); u32 tmp; tmp = dw_pcie_readl_dbi(imx_pcie->pci, offset + PCI_EXP_LNKCAP); @@ -999,7 +999,7 @@ static int imx_pcie_start_link(struct dw_pcie *pci) { struct imx_pcie *imx_pcie = to_imx_pcie(pci); struct device *dev = pci->dev; - u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset = dw_pcie_get_pcie_cap(pci); u32 tmp; int ret; -- 2.43.0