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(unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wD3Dz_umOBqUsqlCw--.64541S6; Tue, 27 Oct 2026 20:28:35 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com>, Frank Li Subject: [PATCH v4 04/16] PCI: dwc: layerscape-ep: Use cached PCIe capability offset Date: Tue, 27 Oct 2026 20:28:15 +0800 Message-ID: <20261027122827.2725643-5-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261027122827.2725643-1-18255117159@163.com> References: <20261027122827.2725643-1-18255117159@163.com> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , Precedence: list X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:_____wD3Dz_umOBqUsqlCw--.64541S6 X-Coremail-Antispam: 1Uf129KBjvJXoW7uFyrXr45GF17AF43Cw13XFb_yoW8WF1xpF Z8JF1Ykr18JF4SgFn29a1Dur13GF9xArW7Ja97K3WavFyav3yUG3s0yryrtFn7KFZFkF1a v3y5tFW5uw4rAFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pimLvJUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6xM12GrgmPMXzgAA3t X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, FROM_LOCAL_DIGITS,FROM_LOCAL_HEX,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Replace the dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) calls in ls_pcie_ep_probe() and ls_pcie_ep_event_handler() with dw_pcie_get_pcie_cap(). The probe reads the Link Capabilities register to save the values configured by the Reset Configuration Word anyway, so the offset is cached there. The link down event handler runs in hardirq context and can then simply reuse the cached value instead of walking the capability list every time the link goes down. Reviewed-by: Frank Li Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index 527c57114dcf..113be247b01b 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -84,7 +84,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) if (val & PEX_PF0_PME_MES_DR_LUD) { - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset = dw_pcie_get_pcie_cap(pci); /* * The values of the Maximum Link Width and Supported Link @@ -268,7 +268,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset = dw_pcie_get_pcie_cap(pci); pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); ret = dw_pcie_ep_init(&pci->ep); -- 2.43.0