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From: phucduc.bui@gmail.com
To: Shengjiu Wang <shengjiu.wang@gmail.com>,
	Shengjiu Wang <shengjiu.wang@nxp.com>,
	Xiubo Li <Xiubo.Lee@gmail.com>,
	Fabio Estevam <festevam@gmail.com>,
	Nicolin Chen <nicoleotsuka@gmail.com>,
	Mark Brown <broonie@kernel.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>,
	Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,
	linuxppc-dev@lists.ozlabs.org, linux-sound@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	bui duc phuc <phucduc.bui@gmail.com>
Subject: [PATCH v2 10/10] ASoC: fsl_sai: Don't write CHMOD to the other direction's xCR4
Date: Thu,  5 Nov 2026 17:42:37 +0700	[thread overview]
Message-ID: <20261105104237.38542-11-phucduc.bui@gmail.com> (raw)
In-Reply-To: <20261105104237.38542-1-phucduc.bui@gmail.com>

From: bui duc phuc <phucduc.bui@gmail.com>

When the current direction is synced to the other one, hw_params()
also writes the frame configuration to the other direction's xCR4.
The mask includes CHMOD, whose value is set by the current direction
(Tx only) but written to the other one, so it is wrong:
- TCR4[CHMOD] is cleared, while Tx needs it set (output mode).
- RCR4 bit 5 is set, while it is reserved and must be written as 0.

CHMOD is not part of the frame configuration, so drop it from the mask.

Fixes: f4c4b1bb2f5a ("ASoC: fsl_sai: Set SAI Channel Mode to Output Mode")
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
 sound/soc/fsl/fsl_sai.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index c61703ddb6f8..430e896d064e 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -720,8 +720,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
 
 	if (fsl_sai_dir_is_synced(sai, adir)) {
 		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
-				   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
-				   FSL_SAI_CR4_CHMOD_MASK,
+				   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
 				   val_cr4);
 		regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
 				   FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
-- 
2.43.0



      parent reply	other threads:[~2026-11-05 10:44 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-05 10:42 [PATCH v2 00/10] ASoC: fsl_sai: Address several issues in the driver phucduc.bui
2026-11-05 10:42 ` [PATCH v2 01/10] ASoC: fsl_sai: Fix PM QoS cleanup on resume failure phucduc.bui
2026-11-05 10:42 ` [PATCH v2 02/10] ASoC: fsl_sai: Use optional clock getter for MCLKs phucduc.bui
2026-11-05 10:42 ` [PATCH v2 03/10] ASoC: fsl_sai: Remove redundant error messages phucduc.bui
2026-11-05 10:42 ` [PATCH v2 04/10] ASoC: fsl_sai: Propagate device tree property read errors phucduc.bui
2026-11-05 10:42 ` [PATCH v2 05/10] ASoC: fsl_sai: Drop redundant dataline mask AND phucduc.bui
2026-11-05 10:42 ` [PATCH v2 06/10] ASoC: fsl_sai: Warn if TE/RE does not clear on disable phucduc.bui
2026-11-05 10:42 ` [PATCH v2 07/10] ASoC: fsl_sai: Clarify fsl_sai_dir_is_synced() documentation phucduc.bui
2026-11-05 10:42 ` [PATCH v2 08/10] ASoC: fsl_sai: Check regmap_read() return value in ISR phucduc.bui
2026-11-05 10:42 ` [PATCH v2 09/10] ASoC: fsl_sai: Reject bclk ratio smaller than slot width phucduc.bui
2026-11-05 10:42 ` phucduc.bui [this message]

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