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bh=L+Hzdt+LObwzKPIKo4htZh/cma3z4S09Q2AYbp2zhRQ=; b=acrz2jDBeH5iI4KbW1VFpKoDLUDnliMN9u2PNdkj02YxM9SYvxw7z311lTaWhWc1Gj R4BSfQlcA6nwaDNBLlg2msZyB5dawbznYW5W/Uc9UefpNcAIFudNGWcpcyP4mQFltt+o hUiodpYMEqlqHXabBoNvI8OO72QgLwTXlc+YgT+STk/Cel4OgzTNKVkHEF1kd7OJXlOQ OAbhTvshKYSoXfIu0a/92q/pTudyrMgAM3I3FPHOLbAFRBZj3n31HNuDFbzvuhdx2tLD SpDIltmpT49G7rm4TzRRsSC0vfmBoVrqg6JqT/gsumOt6g/ZzD+zCnDJNYrxXkW+/unF e1Ow== X-Forwarded-Encrypted: i=1; AKwUvBwy/IUCqIwimEGPp1ke/joZie03RWK/VH5Nc0Y97oBrFlrx6dQfk0UoAK2Gqmz+tNUt8bj5Geh+pccRJz0=@lists.ozlabs.org X-Gm-Message-State: APuU4Z9QK1gl+jJu/ZCPvmlDS/LC1reYW8IjZO+uSPiCjVhFmjA0Aqji zQ+faRTpod4vzFwz7RIK2AV+vNJp+2BkFUlKv5cFToa8rPr1d0ZX1GzPalnpTqJuqQGMdzpzsm9 abR8Ej7VCmUHD/Q== X-Received: from iozd24.prod.google.com ([2002:a05:6602:3298:b0:9c7:85f4:7637]) (user=dmatlack job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6808:23cf:b0:532:d9f5:1de6 with SMTP id 5614622812f47-567e182dc9fmr636250b6e.65.1793925786350; Thu, 05 Nov 2026 16:43:06 -0800 (PST) Date: Fri, 6 Nov 2026 00:42:09 +0000 In-Reply-To: <20261106004218.604799-1-dmatlack@google.com> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , Precedence: list X-Archived-By: Mime-Version: 1.0 References: <20261106004218.604799-1-dmatlack@google.com> X-Mailer: git-send-email 2.56.0.455.g6c5a503b38-goog Message-ID: <20261106004218.604799-9-dmatlack@google.com> Subject: [PATCH v2 08/17] PCI/AER: Save AER state in the saved capability store From: David Matlack To: kexec@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Cc: Alexander Graf , Alex Williamson , Bjorn Helgaas , David Matlack , Jason Gunthorpe , Jonathan Corbet , Josh Hilke , Lukas Wunner , Mahesh J Salgaonkar , Mike Rapoport , "Oliver O'Halloran" , Pasha Tatashin , Pratyush Yadav , Randy Dunlap , Samiullah Khawaja , Shuah Khan , Vipin Sharma Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Save and restore the AER mask, severity, capability and root command registers through the per-device saved capability store instead of a private pci_cap_saved_state buffer. Describe the registers in aer_saved_regs[] and drive the reservation, save, and restore loops from it. Previously the three had to be kept in the same order by hand, and pci_aer_init() encoded the register count as a bare 4 or 5. Reserve the registers in pci_reserve_aer_state(), called from pci_aer_init(), and report a refused reservation. pci_aer_init() ignored the return value of pci_add_ext_cap_save_buffer(), so a failed allocation left AER state unsaved without any message. An allocation failure is now reported once by pci_saved_caps_finalize(). No other functional change intended. Signed-off-by: David Matlack --- drivers/pci/pcie/aer.c | 85 +++++++++++++++++++++++------------------- 1 file changed, 46 insertions(+), 39 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index d8dcd238fda1..25436bcf9fb9 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -352,54 +352,68 @@ int pci_aer_clear_status(struct pci_dev *dev) return pci_aer_raw_clear_status(dev); } -void pci_save_aer_state(struct pci_dev *dev) +/* + * AER registers saved and restored by the PCI core. PCI_ERR_ROOT_COMMAND is + * only implemented by Root Ports and Root Complex Event Collectors (PCIe + * r6.0, sec 7.8.4.9) and so must come last. + */ +static const u16 aer_saved_regs[] = { + PCI_ERR_UNCOR_MASK, + PCI_ERR_UNCOR_SEVER, + PCI_ERR_COR_MASK, + PCI_ERR_CAP, + PCI_ERR_ROOT_COMMAND, +}; + +static unsigned int aer_nr_saved_regs(struct pci_dev *dev) { - int aer = dev->aer_cap; - struct pci_cap_saved_state *save_state; - u32 *cap; + if (pcie_cap_has_rtctl(dev)) + return ARRAY_SIZE(aer_saved_regs); - if (!aer) - return; + return ARRAY_SIZE(aer_saved_regs) - 1; +} - save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); - if (!save_state) +void pci_save_aer_state(struct pci_dev *dev) +{ + unsigned int i; + + if (!dev->aer_cap) return; - cap = &save_state->cap.data[0]; - pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++); - pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++); - pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++); - pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++); - if (pcie_cap_has_rtctl(dev)) - pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++); + for (i = 0; i < aer_nr_saved_regs(dev); i++) + pci_save_cap_dword(dev, dev->aer_cap + aer_saved_regs[i]); } void pci_restore_aer_state(struct pci_dev *dev) { - int aer = dev->aer_cap; - struct pci_cap_saved_state *save_state; - u32 *cap; + unsigned int i; - if (!aer) + if (!dev->aer_cap) return; - save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); - if (!save_state) - return; + for (i = 0; i < aer_nr_saved_regs(dev); i++) + pci_restore_cap_dword(dev, dev->aer_cap + aer_saved_regs[i]); +} - cap = &save_state->cap.data[0]; - pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++); - pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++); - pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++); - pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++); - if (pcie_cap_has_rtctl(dev)) - pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++); +static void pci_reserve_aer_state(struct pci_dev *dev) +{ + unsigned int i; + int rc; + + for (i = 0; i < aer_nr_saved_regs(dev); i++) { + unsigned int off = dev->aer_cap + aer_saved_regs[i]; + + rc = pci_reserve_saved_cap(dev, off, sizeof(u32)); + if (rc) { + pci_err(dev, "unable to reserve AER save state (%pe)\n", + ERR_PTR(rc)); + return; + } + } } void pci_aer_init(struct pci_dev *dev) { - int n; - dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); if (!dev->aer_cap) return; @@ -415,14 +429,7 @@ void pci_aer_init(struct pci_dev *dev) ratelimit_state_init(&dev->aer_info->nonfatal_ratelimit, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); - /* - * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER, - * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event - * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r6.0, sec - * 7.8.4.9). - */ - n = pcie_cap_has_rtctl(dev) ? 5 : 4; - pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n); + pci_reserve_aer_state(dev); /* * Advisory Non-Fatal Errors are masked by default (PCIe r7.0, sec -- 2.56.0.455.g6c5a503b38-goog