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Sat, 07 Nov 2026 05:50:15 -0800 (PST) Received: from mi-OptiPlex-7060.mioffice.cn ([43.224.245.234]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36fa922c6c7sm21280820eec.10.2026.11.07.05.50.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Nov 2026 05:50:14 -0800 (PST) From: Wen Jiang To: akpm@linux-foundation.org, catalin.marinas@arm.com, will@kernel.org, urezki@gmail.com, linux-mm@kvack.org Cc: baohua@kernel.org, dev.jain@arm.com, ryan.roberts@arm.com, anshuman.khandual@arm.com, david@kernel.org, rppt@kernel.org, leo.yan@arm.com, xueyuan.chen21@gmail.com, chleroy@kernel.org, maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, ajd@linux.ibm.com, jiangwen6@xiaomi.com, jiangwenxiaomi@gmail.com, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v12 02/10] powerpc/8xx: add vmap_pte_set_huge() Date: Sat, 7 Nov 2026 21:49:45 +0800 Message-Id: <20261107134953.748622-3-jiangwenxiaomi@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261107134953.748622-1-jiangwenxiaomi@gmail.com> References: <20261107134953.748622-1-jiangwenxiaomi@gmail.com> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , Precedence: list X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_PASS,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Wen Jiang vmap installs PTE-level block mappings (SZ_16K/SZ_512K on powerpc/8xx) by reusing set_huge_pte_at(), a HugeTLB helper gated by CONFIG_HUGETLB_PAGE. This makes the feature silently unavailable on CONFIG_HUGETLB_PAGE=n kernels and couples mm/vmalloc.c to HugeTLB internals it does not otherwise need. Add vmap_pte_set_huge() to powerpc/8xx, next to the existing pmd_clear_huge()/pud_clear_huge() in mm/nohash/8xx.c. It builds the huge PTE and writes it into the backing cells directly, without going through set_huge_pte_at(), so it does not depend on CONFIG_HUGETLB_PAGE. No vmap_pte_clear_huge() is needed: 8xx does not implement arch_vmap_pte_range_unmap_size(), so the vmap unmap path never takes the PTE-clearing branch. In practice PPC_8xx selects HUGETLBFS unconditionally, so CONFIG_HUGETLB_PAGE=n does not occur there today; this is a decoupling cleanup rather than a new configuration. There is no caller yet: mm/vmalloc.c is converted later in this series, once the generic fallbacks are in place. Signed-off-by: Wen Jiang Reviewed-by: Christophe Leroy (CS GROUP) --- arch/powerpc/include/asm/nohash/32/pte-8xx.h | 4 +++ arch/powerpc/mm/nohash/8xx.c | 29 ++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/powerpc/include/asm/nohash/32/pte-8xx.h b/arch/powerpc/include/asm/nohash/32/pte-8xx.h index e2ea8ba9f8cae..141336d30cc76 100644 --- a/arch/powerpc/include/asm/nohash/32/pte-8xx.h +++ b/arch/powerpc/include/asm/nohash/32/pte-8xx.h @@ -235,6 +235,10 @@ static inline pte_t ptep_get(pte_t *ptep) } #endif /* CONFIG_PPC_16K_PAGES */ +#define __HAVE_ARCH_VMAP_PTE_SET_HUGE +void vmap_pte_set_huge(pte_t *ptep, unsigned long addr, phys_addr_t phys, + pgprot_t prot, unsigned long size); + #endif #endif /* __KERNEL__ */ diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c index a9d3f4729eada..b12e2829c08ed 100644 --- a/arch/powerpc/mm/nohash/8xx.c +++ b/arch/powerpc/mm/nohash/8xx.c @@ -220,3 +220,32 @@ int pmd_clear_huge(pmd_t *pmd) { return 0; } + +/* + * vmap PTE-level block mapping. Sets a present kernel mapping directly, + * so unlike set_huge_pte_at() it needs neither CONFIG_HUGETLB_PAGE nor + * set_pte_filter() (a no-op for non-exec kernel mappings). + */ +void vmap_pte_set_huge(pte_t *ptep, unsigned long addr, phys_addr_t phys, + pgprot_t prot, unsigned long size) +{ + pmd_t *pmdp = pmd_off(&init_mm, addr); + pte_t pte = pfn_pte(PHYS_PFN(phys), prot); + pte_basic_t val; + pte_basic_t *entry = (pte_basic_t *)ptep; + int num, i; + + pte = arch_make_huge_pte(pte, ilog2(size), 0); + val = pte_val(pte); + + /* + * Make sure hardware valid bit is not set. We don't do + * tlb flush for this update. + */ + VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep)); + + num = number_of_cells_per_pte(pmdp, val, 1); + + for (i = 0; i < num; i++, entry++, val += SZ_4K) + *entry = val; +} -- 2.34.1