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Mon, 09 Nov 2026 17:47:16 -0800 (PST) Received: from localhost ([2600:1702:7a90:6f9f:8bc4:8aec:108d:7a04]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8b3933a1cf3sm8399777b3.15.2026.11.09.17.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 17:47:15 -0800 (PST) From: Matt Turner Date: Mon, 09 Nov 2026 20:47:06 -0500 Subject: [PATCH 7/8] powerpc/perf: Use SIAR for sample addresses on 32-bit X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , Precedence: list X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261109-ppc32-perf-v1-7-a6e8a55b3b48@gmail.com> References: <20261109-ppc32-perf-v1-0-a6e8a55b3b48@gmail.com> In-Reply-To: <20261109-ppc32-perf-v1-0-a6e8a55b3b48@gmail.com> To: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , "Ritesh Harjani (IBM)" , Shrikanth Hegde , Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Matt Turner X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4209; i=mattst88@gmail.com; h=from:subject:message-id; bh=IV87DZUvmybjN6JB+MieMd8HoMSlN7JVQzsooFUy8EA=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLI+lU85dW3Djx/3Lh7g9o7pbNXUr42b9zf47lJtEae6n b9U+6/KdnxkYRDjYpgppsgSt16RZVbbjqU+p6V/wcxhZQIZIi3SwAAELAx8uYl5pUY6Rnqm2oZ6 hkCGjlE8RE6PQSOzuLg0tUg3raDIIS+/JLEkMz+vWC+/IDWvIL1ALy0zrSQjI7+oOBVohF5eaom pq6ObkaGBiaWjhZmThaOpibOzk6GTm6Ojs6uTkaW5iYGzpaOJq6U5AxenAMw1k88xMhzn31w8Qc Vls5z7ep8S302hNn5W9t6/DjmyPfRf8WEOQwPDf5fUlTodM3e+YdapYeI9vTPQ9mNg06qeGUVXq vy2Bl/l5gcA X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_PASS,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 32-bit, perf_read_regs() sets regs->result to 0, so regs_use_siar() is always false and every sample is attributed to the interrupted PC. The MPC7450 family's SIAR holds the address of the last instruction to complete before the performance monitor exception is generated (MPC7450UM Rev. 5, section 11.3.7). The exception can be generated with MSR[EE] = 0 and is taken once EE is set again (section 11.2), so when interrupts are disabled the interrupted PC is wherever they are re-enabled, while SIAR still points into the disabled region. On a 7448, sampling cycles system-wide with --intr-regs=nip during dd, perf bench sched pipe and find, 46% of the kernel samples have SIAR and the interrupted PC in different functions. 13270 samples have their PC on the instruction after the mtmsr that restores interrupts in ata_scsi_queuecmd(), and 11661 of those have SIAR in udelay(). With interrupts enabled SIAR helps less. Sampling a 32-instruction loop with one store and one branch with -c 10007, 99.8% of the samples land at: event interrupted PC SIAR r122 (branches) br + 13 br + 9 r014 (stores) stw + 21 stw + 17 siar_valid() already returns true on 32-bit. Use SIAR for PMU exceptions, and take the user/kernel flags from it too. Move regs_use_siar() above the 32-bit block so that perf_get_misc_flags() can call it. Signed-off-by: Matt Turner --- arch/powerpc/perf/core-book3s.c | 55 +++++++++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 19 deletions(-) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 10ded865583c..e4c8ecddccbd 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -75,6 +75,20 @@ static struct power_pmu *ppmu; */ static unsigned int freeze_events_kernel = MMCR0_FCS; +static bool regs_use_siar(struct pt_regs *regs) +{ + /* + * When we take a performance monitor exception the regs are setup + * using perf_read_regs() which overloads some fields, in particular + * regs->result to tell us whether to use SIAR. + * + * However if the regs are from another exception, eg. a syscall, then + * they have not been setup using perf_read_regs() and so regs->result + * is something random. + */ + return ((TRAP(regs) == INTERRUPT_PERFMON) && regs->result); +} + /* * 32-bit doesn't have MMCRA but does have an MMCR2, * and a few other names are different. @@ -108,13 +122,30 @@ static inline unsigned long perf_ip_adjust(struct pt_regs *regs) return 0; } static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) { } -static inline u32 perf_get_misc_flags(struct pt_regs *regs) -{ - return 0; -} + +/* + * The MPC7450 family's SIAR holds the address of the last instruction to + * complete before the performance monitor exception was generated, so for + * a PMU exception it is closer to the event than the interrupted PC. + */ static inline void perf_read_regs(struct pt_regs *regs) { - regs->result = 0; + regs->result = 1; +} + +static inline u32 perf_get_misc_flags(struct pt_regs *regs) +{ + unsigned long siar; + + if (!regs_use_siar(regs)) + return 0; + + siar = mfspr(SPRN_SIAR); + if (!siar) + return 0; + + return is_kernel_addr(siar) ? PERF_RECORD_MISC_KERNEL : + PERF_RECORD_MISC_USER; } static inline int siar_valid(struct pt_regs *regs) @@ -163,20 +194,6 @@ unsigned long get_pmcs_ext_regs(int idx) return cpuhw->pmcs[idx]; } -static bool regs_use_siar(struct pt_regs *regs) -{ - /* - * When we take a performance monitor exception the regs are setup - * using perf_read_regs() which overloads some fields, in particular - * regs->result to tell us whether to use SIAR. - * - * However if the regs are from another exception, eg. a syscall, then - * they have not been setup using perf_read_regs() and so regs->result - * is something random. - */ - return ((TRAP(regs) == INTERRUPT_PERFMON) && regs->result); -} - /* * Things that are specific to 64-bit implementations. */ -- 2.55.0