From: "Ritesh Harjani (IBM)" <ritesh.list@gmail.com>
To: linuxppc-dev@lists.ozlabs.org
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>,
Michael Ellerman <mpe@ellerman.id.au>,
Nicholas Piggin <npiggin@gmail.com>,
Christophe Leroy <christophe.leroy@csgroup.eu>,
Paul Mackerras <paulus@ozlabs.org>,
"Aneesh Kumar K . V" <aneesh.kumar@kernel.org>,
Donet Tom <donettom@linux.ibm.com>,
Pavithra Prakash <pavrampu@linux.ibm.com>,
"Ritesh Harjani (IBM)" <ritesh.list@gmail.com>
Subject: [PATCH v2 07/11] powerpc/64s/hash: Update directMap page counters for Hash
Date: Thu, 30 Oct 2025 20:27:32 +0530 [thread overview]
Message-ID: <208e6f946d2ba9c1e2b8b4f665728abe5c891e7c.1761834163.git.ritesh.list@gmail.com> (raw)
In-Reply-To: <cover.1761834163.git.ritesh.list@gmail.com>
Update the directMap page counters for Hash. Hash by default always uses
mmu_linear_psize only, for it's directMap. However, once the kernel has
booted and the dmesg log is wrapped over there is no way of knowing the
kernel linear pagesize with Hash mmu. Features like debug_page_alloc can
make mmu_linear_psize to be PAGE_SIZE instead of PMD / PUD mappings. It
would be easier if we have this info printed in proc meminfo similar to
Radix for debugging purposes.
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Paul Mackerras <paulus@ozlabs.org>
Cc: Aneesh Kumar K.V <aneesh.kumar@kernel.org>
Cc: Donet Tom <donettom@linux.ibm.com>
Cc: <linuxppc-dev@lists.ozlabs.org>
Signed-off-by: Ritesh Harjani (IBM) <ritesh.list@gmail.com>
---
arch/powerpc/mm/book3s64/hash_utils.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/powerpc/mm/book3s64/hash_utils.c b/arch/powerpc/mm/book3s64/hash_utils.c
index e63befc96708..31162dbad05c 100644
--- a/arch/powerpc/mm/book3s64/hash_utils.c
+++ b/arch/powerpc/mm/book3s64/hash_utils.c
@@ -47,6 +47,7 @@
#include <asm/mmu.h>
#include <asm/mmu_context.h>
#include <asm/page.h>
+#include <asm/pgalloc.h>
#include <asm/types.h>
#include <linux/uaccess.h>
#include <asm/machdep.h>
@@ -449,6 +450,7 @@ static __init void hash_kfence_map_pool(void)
{
unsigned long kfence_pool_start, kfence_pool_end;
unsigned long prot = pgprot_val(PAGE_KERNEL);
+ unsigned int pshift = mmu_psize_defs[mmu_linear_psize].shift;
if (!kfence_pool)
return;
@@ -459,6 +461,7 @@ static __init void hash_kfence_map_pool(void)
BUG_ON(htab_bolt_mapping(kfence_pool_start, kfence_pool_end,
kfence_pool, prot, mmu_linear_psize,
mmu_kernel_ssize));
+ update_page_count(mmu_linear_psize, KFENCE_POOL_SIZE >> pshift);
memblock_clear_nomap(kfence_pool, KFENCE_POOL_SIZE);
}
@@ -1234,6 +1237,7 @@ int hash__create_section_mapping(unsigned long start, unsigned long end,
int nid, pgprot_t prot)
{
int rc;
+ unsigned int pshift = mmu_psize_defs[mmu_linear_psize].shift;
if (end >= H_VMALLOC_START) {
pr_warn("Outside the supported range\n");
@@ -1251,17 +1255,22 @@ int hash__create_section_mapping(unsigned long start, unsigned long end,
mmu_kernel_ssize);
BUG_ON(rc2 && (rc2 != -ENOENT));
}
+ update_page_count(mmu_linear_psize, (end - start) >> pshift);
return rc;
}
int hash__remove_section_mapping(unsigned long start, unsigned long end)
{
+ unsigned int pshift = mmu_psize_defs[mmu_linear_psize].shift;
+
int rc = htab_remove_mapping(start, end, mmu_linear_psize,
mmu_kernel_ssize);
if (resize_hpt_for_hotplug(memblock_phys_mem_size()) == -ENOSPC)
pr_warn("Hash collision while resizing HPT\n");
+ if (!rc)
+ update_page_count(mmu_linear_psize, -((end - start) >> pshift));
return rc;
}
#endif /* CONFIG_MEMORY_HOTPLUG */
@@ -1304,6 +1313,7 @@ static void __init htab_initialize(void)
unsigned long prot;
phys_addr_t base = 0, size = 0, end, limit = MEMBLOCK_ALLOC_ANYWHERE;
u64 i;
+ unsigned int pshift = mmu_psize_defs[mmu_linear_psize].shift;
DBG(" -> htab_initialize()\n");
@@ -1404,6 +1414,8 @@ static void __init htab_initialize(void)
BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
prot, mmu_linear_psize, mmu_kernel_ssize));
+
+ update_page_count(mmu_linear_psize, size >> pshift);
}
hash_kfence_map_pool();
memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
@@ -1425,6 +1437,8 @@ static void __init htab_initialize(void)
BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
__pa(tce_alloc_start), prot,
mmu_linear_psize, mmu_kernel_ssize));
+ update_page_count(mmu_linear_psize,
+ (tce_alloc_end - tce_alloc_start) >> pshift);
}
--
2.51.0
next prev parent reply other threads:[~2025-10-30 15:00 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-30 14:57 [PATCH v2 00/11] powerpc/book3s64: Hash / SLB fixes & improvements Ritesh Harjani (IBM)
2025-10-30 14:57 ` [PATCH v2 01/11] powerpc/64s/slb: Fix SLB multihit issue during SLB preload Ritesh Harjani (IBM)
2025-10-30 14:57 ` [PATCH v2 02/11] powerpc/64s/hash: Restrict stress_hpt_struct memblock region to within RMA limit Ritesh Harjani (IBM)
2025-10-30 14:57 ` [PATCH v2 03/11] powerpc/64s/ptdump: Fix kernel_hash_pagetable dump for ISA v3.00 HPTE format Ritesh Harjani (IBM)
2025-10-30 14:57 ` [PATCH v2 04/11] powerpc/64s/hash: Fix phys_addr_t printf format in htab_initialize() Ritesh Harjani (IBM)
2025-10-30 14:57 ` [PATCH v2 05/11] powerpc/64s/hash: Improve hash mmu printk messages Ritesh Harjani (IBM)
2025-10-30 14:57 ` [PATCH v2 06/11] powerpc/64s/hash: Hash hpt_order should be only available with Hash MMU Ritesh Harjani (IBM)
2025-10-30 14:57 ` Ritesh Harjani (IBM) [this message]
2025-10-30 14:57 ` [PATCH v2 08/11] powerpc/64s/pgtable: Enable directMap counters in meminfo for Hash Ritesh Harjani (IBM)
2025-10-30 14:57 ` [PATCH v2 09/11] powerpc/ptdump: Dump PXX level info for kernel_page_tables Ritesh Harjani (IBM)
2025-10-30 14:57 ` [PATCH v2 10/11] powerpc/64s/slb: Make preload_add return type as void Ritesh Harjani (IBM)
2025-10-30 14:57 ` [PATCH v2 11/11] powerpc/64s/slb: Add no_slb_preload early cmdline param Ritesh Harjani (IBM)
[not found] ` <2197e5654ffff3960ccd4563f88e9396@imap.linux.ibm.com>
2025-11-08 2:34 ` Ritesh Harjani
2025-11-23 7:08 ` [PATCH v2 00/11] powerpc/book3s64: Hash / SLB fixes & improvements Madhavan Srinivasan
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