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[124.171.107.241]) by smtp.gmail.com with UTF8SMTPSA id t4sm12976444pjs.12.2021.03.22.01.39.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Mar 2021 01:39:33 -0700 (PDT) Message-ID: <21be26e7-d8c9-6681-d89d-4ffdf46d23f7@ozlabs.ru> Date: Mon, 22 Mar 2021 19:39:29 +1100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:87.0) Gecko/20100101 Thunderbird/87.0 Subject: Re: [PATCH v3 20/41] KVM: PPC: Book3S HV P9: Move setting HDEC after switching to guest LPCR Content-Language: en-US To: Nicholas Piggin , kvm-ppc@vger.kernel.org References: <20210305150638.2675513-1-npiggin@gmail.com> <20210305150638.2675513-21-npiggin@gmail.com> From: Alexey Kardashevskiy In-Reply-To: <20210305150638.2675513-21-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 06/03/2021 02:06, Nicholas Piggin wrote: > LPCR[HDICE]=0 suppresses hypervisor decrementer exceptions on some > processors, so it must be enabled before HDEC is set. Educating myself - is not it a processor bug when it does not suppress hdec exceptions with HDICE=0? Also, why do we want to enable interrupts before writing HDEC? Enabling it may cause an interrupt right away a Anyway whatever the answers are, this is not changed by this patch and the change makes sense so Reviewed-by: Alexey Kardashevskiy > Rather than set it in the host LPCR then setting HDEC, move the HDEC > update to after the guest MMU context (including LPCR) is loaded. > There shouldn't be much concern with delaying HDEC by some 10s or 100s > of nanoseconds by setting it a bit later. > > Signed-off-by: Nicholas Piggin > --- > arch/powerpc/kvm/book3s_hv.c | 19 +++++++------------ > 1 file changed, 7 insertions(+), 12 deletions(-) > > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index 1f2ba8955c6a..ffde1917ab68 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -3505,20 +3505,9 @@ static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu *vcpu, u64 time_limit, > host_dawrx1 = mfspr(SPRN_DAWRX1); > } > > - /* > - * P8 and P9 suppress the HDEC exception when LPCR[HDICE] = 0, > - * so set HDICE before writing HDEC. > - */ > - mtspr(SPRN_LPCR, kvm->arch.host_lpcr | LPCR_HDICE); > - isync(); > - > hdec = time_limit - mftb(); > - if (hdec < 0) { > - mtspr(SPRN_LPCR, kvm->arch.host_lpcr); > - isync(); > + if (hdec < 0) > return BOOK3S_INTERRUPT_HV_DECREMENTER; > - } > - mtspr(SPRN_HDEC, hdec); > > if (vc->tb_offset) { > u64 new_tb = mftb() + vc->tb_offset; > @@ -3564,6 +3553,12 @@ static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu *vcpu, u64 time_limit, > > switch_mmu_to_guest_radix(kvm, vcpu, lpcr); > > + /* > + * P9 suppresses the HDEC exception when LPCR[HDICE] = 0, > + * so set guest LPCR (with HDICE) before writing HDEC. > + */ > + mtspr(SPRN_HDEC, hdec); > + > mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0); > mtspr(SPRN_SRR1, vcpu->arch.shregs.srr1); > > -- Alexey