From: "Sauce.Cheng" <chmhou@sina.com>
To: linuxppc-dev@ozlabs.org
Subject: Re: question : DMA of PCI bridge
Date: Thu, 21 May 2009 20:24:03 -0700 (PDT) [thread overview]
Message-ID: <23663840.post@talk.nabble.com> (raw)
In-Reply-To: <4A14D12D.4050302@ovro.caltech.edu>
>
> in the manual reference charpter 9.13 DMA, source and destination address
> If you are DMAing from an internal peripheral, then it's
> width will be hard-coded and can be read from the user-manual.
you mean it will be set by hard circuit ? maybe i should talk with your hard
engineer.
but as you say, the width will be hard-coded, mean that the width can not be
changed ?
it can fetch 16 bits to 32bits, can not tetch 16bits to 16bits ?
i am sorry about my poor English, i am not sure if i expressed clearly
> If you are DMAing from a local bus then the local bus definition
> should determine what happens. For example, on the MPC8349, you
> can put 16-bit flash on the local bus, and configure the local
> bus controller to know that it is 16-bits wide. A 32-bit access
> by the CPU or DMA controller will generate two reads on the
> local bus.
that's right, BRx and ORx should be configured for setting width, but that
is bus width, not data width. or bus width should be equal to data width
what fetch from the bus ?
> You can investigate to see whether the MPC8247 works similarly.
all right, i will , thanks a lot
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prev parent reply other threads:[~2009-05-22 3:24 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-20 3:19 question : DMA of PCI bridge Sauce.Cheng
2009-05-20 3:51 ` David Hawkins
2009-05-21 3:42 ` Sauce.Cheng
2009-05-21 3:57 ` David Hawkins
2009-05-22 3:24 ` Sauce.Cheng [this message]
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