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Mon, 23 Feb 2026 03:49:37 +0000 Received: from DS0PR12MB8245.namprd12.prod.outlook.com ([fe80::e7c5:cfca:a597:7fa4]) by DS0PR12MB8245.namprd12.prod.outlook.com ([fe80::e7c5:cfca:a597:7fa4%4]) with mapi id 15.20.9632.017; Mon, 23 Feb 2026 03:49:37 +0000 Message-ID: <236a5eeb-e22e-4973-a693-319c1376f9d0@nvidia.com> Date: Mon, 23 Feb 2026 09:19:17 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/9] PCI: endpoint differentiate between disabled and reserved BARs To: Niklas Cassel Cc: Koichiro Den , Damien Le Moal , linux-pci@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@axis.com, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-tegra@vger.kernel.org, linux-kselftest@vger.kernel.org, Manivannan Sadhasivam , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Arnd Bergmann , Greg Kroah-Hartman , Vignesh Raghavendra , Siddharth Vadapalli , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Richard Zhu , Lucas Stach , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson , Jingoo Han , Heiko Stuebner , Srikanth Thokala , Marek Vasut , Yoshihiro Shimoda , Geert Uytterhoeven , Magnus Damm , Christian Bruel , Maxime Coquelin , Alexandre Torgue , Thierry Reding , Jonathan Hunter , Kunihiko Hayashi , Masami Hiramatsu , Shuah Khan References: <20260217212707.2450423-11-cassel@kernel.org> Content-Language: en-US X-Nvconfidentiality: public From: Manikanta Maddireddy In-Reply-To: <20260217212707.2450423-11-cassel@kernel.org> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?S2JSYnRhbVhGWHFtWDBVTTZyTGgvbGsxSkJXUGk1U3VYU2RVYlFFL2RxWllV?= =?utf-8?B?cVF3dWIrRmZnWFhVL01sdE9xLzhrZUFaNEF0V1NoenJlcHUyVUxLb2hvOXJM?= =?utf-8?B?U296UHZzZkw4WGhnZTk5MTQ0bGNYMlduU3VLeWh1VFhpcjJZS0JvanBDSDVW?= =?utf-8?B?cGpuK3c0Vmd2blBtYXFaTXhWb29aSHg2eEFINzd1RVRWdWN3eVl2WUNuNGFj?= =?utf-8?B?Q0xpUzArUVpoWmpheHk2SFBwY090WWRyZmFTZWJ3eVk2VGcxaERxU2V1c0k2?= =?utf-8?B?ZlZHWU4waHgveVNBMVh5TXFHaDJEOWkxb01CSFY4cUJOYWpsZlVlbXNWR2FW?= =?utf-8?B?WHhwYWRZZ2J4VTd3d1Z2N2NOdHQ5VWlQOFpHN2VoVjdQdWFNdHJVWm04YnA4?= =?utf-8?B?bjZ4dkoybFBzQWEyYjlGVEN4WHhzYWd6TTNja05zdmRScHJTWVVrL29KM1lj?= =?utf-8?B?RjM5YjJSRktlYmV5WXB3L0ZQSlpET1JSQ1JxbGdRbVRuU0JlRE5kc0Qrakk1?= =?utf-8?B?L0xJMkdBWnBQNWo3WWxnSU9xOS9Zelg2VitscU1xZHhnOE9DaG5DcEV6VWl3?= =?utf-8?B?SmxyTm1IbEhVV2Q4SXExVVdZQUo0aW9ZeVFMRnRMZ1RyTTQrVE5CTy9EVldZ?= =?utf-8?B?eENIcWFEdGRPdGpwZzdieWlIWHVqd1BEUGhCcTU1L1k2WmhNYUFCMU1KZXBI?= =?utf-8?B?c1NUNW5LTW1xcjNxeU9ENVluak1mMmZoVEp2R1VWaCswc3FrZnpGN3BPM28x?= =?utf-8?B?cnN3SzBjN1p4QzRaWE1Lc3h0SUs3dlI4cXlQWHR6c3pxZit6SnZVRlBndlls?= =?utf-8?B?ZnVSYTJYNEExTW1UMENyRGoweTN6Yy81NVJza3FYek1UT3g0cEYydDhyOE1R?= =?utf-8?B?Qm4wdVRQNlh2UnJETzFVSWhBMXMrTkhmd1JHd1U5NzRQYWNuMGRoZ2VmUC95?= =?utf-8?B?OUxld3NhamxEYTNmeG4rWW5lN01wb0lzREdFL0dwUXFGTVdUb0ZRTEdVODUz?= =?utf-8?B?WDkvb2hCZzQyL2NsZXB1WG0rNnpKWVhpZW1GQk5TNU1INWNtNXBNOGxJQ0V4?= =?utf-8?B?STBFY1pjbklQVnZJL0IzdnQyNjhNZXl1SmVPRlErZVRSakRXN1cva3NGTFNp?= =?utf-8?B?aGtyR2c1V2ZmUlZjQjJHMXgwRG1NcCtHVGxCTlhzcEUxQTcvcWdQOW9rcXBi?= =?utf-8?B?OUZMdy9XVU1LKzNrdURvdkduTWxLdHJqb3VDTHF4RHVJb1lWbmJ2a0tLcTFK?= =?utf-8?B?Z3MrMGNobEpKUU1WZTM4S290N1N6VUxQSWJNTUVxa0t1cVlkd1AwVVNhU3dX?= =?utf-8?B?OFVSY2NVR1Y4NExOMkg5N1kxV2NSM1ozOFpzRTQ1ZnJoRHRVVWk2MUhYTFp0?= =?utf-8?B?Snk2eHpvaXJkbjZvVnBUVGZlaGxha1o1c3gyVmF5NFJPK1Y2WEQwSFhpcUsz?= =?utf-8?B?MmsrQks1NndoUlA1Q1M5eTB1cHgxdnFWNzlCTldXMzcydURBK1NIR1NYS1FC?= =?utf-8?B?dXNWbUtJVDFPd1lnTVFMOFZQNXhCM1V1NGVFcURUcmluaUpyaXVGRlFjME9n?= =?utf-8?B?RzdGdzZtVit3NVRJVW9laEdLV21kbHFHdG5ITWhNbU1aekVLSEVEMyt3RktQ?= =?utf-8?B?QmdiclNTNkhQSFcwZFMyU2JEbVlMV1NPQ0g4YmtWQmNDcFZjdHdmZzBNUThO?= =?utf-8?B?aFF4RHhrWENpd2xETFhuaEdoS2ZqbEV2MlVsd2ZMc0dmalRuNHc3RENJNFla?= =?utf-8?B?WjYxTW04Vlp2Q1VsMGtkbFhkMFlyVWZ2SW5EUFgzMVJkelVmbTJwd3hrbW1B?= =?utf-8?B?M0RTWlNWTDBhSDZ3RXpSMnliR2I1QnQ5Tkppejh0aTRMVzVPZDQ0bXU2RlNo?= =?utf-8?B?VmVlc0NyUkgwZVcyUDRMck4rSjV3VE5kQ0ZZaXNhVDRXR1BTMlZESlIyVW53?= =?utf-8?B?czluaEo0aitFMTIzWVpIelRqZzBrQUIxY1BLdFkrSHlaRUg4SlpZTWFqZ0xt?= =?utf-8?B?ZUNhOE9rUVRMVUZHWTdNaXZreUdWYUIzdjJwRmFzLzFGY2FPd1B6bnA4UEdz?= =?utf-8?B?ZWtVYit3eEZIYmVEa0pZbmlLeUQ5T29tdUlFTkhFd1VqcjBHZUMxczdUSmpC?= =?utf-8?B?Y1FJUUxLdkJjS1pGNzJPc0FUMU40NVBGU0szY1hqMkYwSXJNMzZKM1NJNWNV?= =?utf-8?B?QVAxbDNqYlRralRFeGpFcVpMR3JmVFI0MWw2cFJYRXc5ckxyNG52L1FKK3VS?= =?utf-8?B?V0VlQmRKclYzRk04amc2bmNHdzBwVDZsZ2Q1T0tkTjVZcXI3eWpDV3J4K3Ru?= =?utf-8?B?M0poSlhYTWVPbm9YR2ZYTWp1RWU1czRwemZDSFRyamsxOEIxRlhpNjdlZVZ5?= =?utf-8?Q?X9p8wdh0avJsP+dI=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: b9b481c2-f603-4102-79d8-08de728e90cb X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB8245.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 03:49:37.6692 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Tzq2nK2r6dC5N37IyB3SjAtlJ2nlw0fKZESv9XnyqwR2LVXUhA+oHS5AtRU89vylSYS6BNxKY+srWljpoaELWg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6452 On 18/02/26 2:57 am, Niklas Cassel wrote: > Hello all, > > This series is written in response to the patch series from > Manikanta Maddireddy that was posted here: > https://lore.kernel.org/linux-pci/291dab65-3fa6-4fc8-90a2-4ad608ca015c@nvidia.com/T/#t > > The reasons why I decided to post this a new series was because the series > above: > > 1) Adds PCI device and vendor specific code to > drivers/misc/pci_endpoint_test.c. We've worked hard to make sure that > device specific quirks/limitations are communicated via the Capabilities > register, so let's do the same for reserved BARs. > > 2) My review comment which suggested to convert all uses of BAR_RESERVED > to BAR_DISABLED (except for pci-keystone.c) was ignored. > > 3) Koichiro has posted a series that allows an EPC driver to define exactly > which hardware backed resources are provided in a BAR_RESERVED BAR. Yet, > this nice improvement was not incorporated. (While Mankata was part of the > discussion, he was not CC:d on the patches that actually implemented this.) > > 4) The selftests should return skip instead of silent success for a > reserved BAR. > > 5) As Mankata points out, but did not address, BAR_RESERVED is quite > ambiguous, so it is better to introduce a new BAR_64BIT_UPPER to more > clearly mark the upper part of a 64-bit BAR as this, rather than reuse > BAR_RESERVED. > > 6) It is possible to remove all the dw_pcie_ep_reset_bar() calls in the > DWC based glue drivers and move it to DWC common code. > > > Because of all of the above, I thought it was just easier to post a series > with all of the above addressed, as it seemed easier to just show what I > meant rather than to try to explain things with words. > > The thing that is missing is to add a patch for pcie-tegra194.c which > converts the BARs to BAR_RESERVED. > Please see patch "PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window" > and do something similar to pcie-tegra194.c. > > If we are missing some resources (right now we only have > PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO), then I think we should simple add that > (e.g. PCI_EPC_BAR_RSVD_MSIX). > > Mankata, it would be nice if you could test this series, and if you could > provide a pcie-tegra194.c patch that adds the sizes of the eDMA regs + > MSI-X table in BAR_2 and BAR_4. > > > Kind regards, > Niklas > > > Koichiro Den (2): > PCI: endpoint: Describe reserved subregions within BARs > PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window > > Niklas Cassel (7): > PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER > PCI: endpoint: Introduce pci_epc_bar_type BAR_DISABLED > PCI: dwc: Replace BAR_RESERVED with BAR_DISABLED in glue drivers > PCI: dwc: Disable BARs in common code instead of in each glue driver > PCI: endpoint: pci-epf-test: Advertise reserved BARs > misc: pci_endpoint_test: Give reserved BARs a distinct error code > selftests: pci_endpoint: Skip reserved BARs > > drivers/misc/pci_endpoint_test.c | 32 ++++++++++++- > drivers/pci/controller/dwc/pci-dra7xx.c | 4 -- > drivers/pci/controller/dwc/pci-imx6.c | 22 +++------ > .../pci/controller/dwc/pci-layerscape-ep.c | 8 +--- > drivers/pci/controller/dwc/pcie-artpec6.c | 4 -- > .../pci/controller/dwc/pcie-designware-ep.c | 24 ++++++++++ > .../pci/controller/dwc/pcie-designware-plat.c | 10 ----- > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 19 +++++--- > drivers/pci/controller/dwc/pcie-keembay.c | 6 +-- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 14 +----- > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 16 ++----- > drivers/pci/controller/dwc/pcie-stm32-ep.c | 10 ----- > drivers/pci/controller/dwc/pcie-tegra194.c | 20 +++------ > drivers/pci/controller/dwc/pcie-uniphier-ep.c | 24 +++------- > drivers/pci/controller/pcie-rcar-ep.c | 6 +-- > drivers/pci/endpoint/functions/pci-epf-test.c | 24 ++++++++++ > drivers/pci/endpoint/pci-epc-core.c | 6 ++- > include/linux/pci-epc.h | 45 +++++++++++++++++-- > .../pci_endpoint/pci_endpoint_test.c | 4 ++ > 19 files changed, 173 insertions(+), 125 deletions(-) > Hi Niklas, I verified this patch series, along with the one linked below, on the Jetson AGX Orin platform: https://lore.kernel.org/linux-pci/20260222193456.2460963-1-mmaddireddy@nvidia.com/T/#t I reviewed the BAR details in the lspci -vvv output—all three BARs are enabled. I also ran pci_endpoint_test, and all tests passed successfully. Thanks, Manikanta