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Thu, 26 Nov 2020 09:00:22 +0000 (GMT) Received: from localhost.localdomain (unknown [9.145.26.176]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 26 Nov 2020 09:00:22 +0000 (GMT) Subject: Re: [PATCH V4 2/5] ocxl: Initiate a TLB invalidate command To: Christophe Lombard , linuxppc-dev@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com, ajd@linux.ibm.com References: <20201125155013.39955-1-clombard@linux.vnet.ibm.com> <20201125155013.39955-3-clombard@linux.vnet.ibm.com> From: Frederic Barrat Message-ID: <25565285-f757-c98f-2db2-af2b117d0b41@linux.ibm.com> Date: Thu, 26 Nov 2020 10:00:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <20201125155013.39955-3-clombard@linux.vnet.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-26_02:2020-11-26, 2020-11-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 phishscore=0 clxscore=1015 impostorscore=0 malwarescore=0 mlxscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 adultscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011260048 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 25/11/2020 16:50, Christophe Lombard wrote: > When a TLB Invalidate is required for the Logical Partition, the following > sequence has to be performed: > > 1. Load MMIO ATSD AVA register with the necessary value, if required. > 2. Write the MMIO ATSD launch register to initiate the TLB Invalidate > command. > 3. Poll the MMIO ATSD status register to determine when the TLB Invalidate > has been completed. > > Signed-off-by: Christophe Lombard > --- Thanks! Acked-by: Frederic Barrat > arch/powerpc/include/asm/pnv-ocxl.h | 51 ++++++++++++++++++++ > arch/powerpc/platforms/powernv/ocxl.c | 69 +++++++++++++++++++++++++++ > 2 files changed, 120 insertions(+) > > diff --git a/arch/powerpc/include/asm/pnv-ocxl.h b/arch/powerpc/include/asm/pnv-ocxl.h > index 60c3c74427d9..9acd1fbf1197 100644 > --- a/arch/powerpc/include/asm/pnv-ocxl.h > +++ b/arch/powerpc/include/asm/pnv-ocxl.h > @@ -3,12 +3,59 @@ > #ifndef _ASM_PNV_OCXL_H > #define _ASM_PNV_OCXL_H > > +#include > #include > > #define PNV_OCXL_TL_MAX_TEMPLATE 63 > #define PNV_OCXL_TL_BITS_PER_RATE 4 > #define PNV_OCXL_TL_RATE_BUF_SIZE ((PNV_OCXL_TL_MAX_TEMPLATE+1) * PNV_OCXL_TL_BITS_PER_RATE / 8) > > +#define PNV_OCXL_ATSD_TIMEOUT 1 > + > +/* TLB Management Instructions */ > +#define PNV_OCXL_ATSD_LNCH 0x00 > +/* Radix Invalidate */ > +#define PNV_OCXL_ATSD_LNCH_R PPC_BIT(0) > +/* Radix Invalidation Control > + * 0b00 Just invalidate TLB. > + * 0b01 Invalidate just Page Walk Cache. > + * 0b10 Invalidate TLB, Page Walk Cache, and any > + * caching of Partition and Process Table Entries. > + */ > +#define PNV_OCXL_ATSD_LNCH_RIC PPC_BITMASK(1, 2) > +/* Number and Page Size of translations to be invalidated */ > +#define PNV_OCXL_ATSD_LNCH_LP PPC_BITMASK(3, 10) > +/* Invalidation Criteria > + * 0b00 Invalidate just the target VA. > + * 0b01 Invalidate matching PID. > + */ > +#define PNV_OCXL_ATSD_LNCH_IS PPC_BITMASK(11, 12) > +/* 0b1: Process Scope, 0b0: Partition Scope */ > +#define PNV_OCXL_ATSD_LNCH_PRS PPC_BIT(13) > +/* Invalidation Flag */ > +#define PNV_OCXL_ATSD_LNCH_B PPC_BIT(14) > +/* Actual Page Size to be invalidated > + * 000 4KB > + * 101 64KB > + * 001 2MB > + * 010 1GB > + */ > +#define PNV_OCXL_ATSD_LNCH_AP PPC_BITMASK(15, 17) > +/* Defines the large page select > + * L=0b0 for 4KB pages > + * L=0b1 for large pages) > + */ > +#define PNV_OCXL_ATSD_LNCH_L PPC_BIT(18) > +/* Process ID */ > +#define PNV_OCXL_ATSD_LNCH_PID PPC_BITMASK(19, 38) > +/* NoFlush – Assumed to be 0b0 */ > +#define PNV_OCXL_ATSD_LNCH_F PPC_BIT(39) > +#define PNV_OCXL_ATSD_LNCH_OCAPI_SLBI PPC_BIT(40) > +#define PNV_OCXL_ATSD_LNCH_OCAPI_SINGLETON PPC_BIT(41) > +#define PNV_OCXL_ATSD_AVA 0x08 > +#define PNV_OCXL_ATSD_AVA_AVA PPC_BITMASK(0, 51) > +#define PNV_OCXL_ATSD_STAT 0x10 > + > int pnv_ocxl_get_actag(struct pci_dev *dev, u16 *base, u16 *enabled, u16 *supported); > int pnv_ocxl_get_pasid_count(struct pci_dev *dev, int *count); > > @@ -31,4 +78,8 @@ int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle); > int pnv_ocxl_map_lpar(struct pci_dev *dev, uint64_t lparid, > uint64_t lpcr, void __iomem **arva); > void pnv_ocxl_unmap_lpar(void __iomem *arva); > +void pnv_ocxl_tlb_invalidate(void __iomem *arva, > + unsigned long pid, > + unsigned long addr, > + unsigned long page_size); > #endif /* _ASM_PNV_OCXL_H */ > diff --git a/arch/powerpc/platforms/powernv/ocxl.c b/arch/powerpc/platforms/powernv/ocxl.c > index 57fc1062677b..9105efcf242a 100644 > --- a/arch/powerpc/platforms/powernv/ocxl.c > +++ b/arch/powerpc/platforms/powernv/ocxl.c > @@ -528,3 +528,72 @@ void pnv_ocxl_unmap_lpar(void __iomem *arva) > iounmap(arva); > } > EXPORT_SYMBOL_GPL(pnv_ocxl_unmap_lpar); > + > +void pnv_ocxl_tlb_invalidate(void __iomem *arva, > + unsigned long pid, > + unsigned long addr, > + unsigned long page_size) > +{ > + unsigned long timeout = jiffies + (HZ * PNV_OCXL_ATSD_TIMEOUT); > + u64 val = 0ull; > + int pend; > + u8 size; > + > + if (!(arva)) > + return; > + > + if (addr) { > + /* load Abbreviated Virtual Address register with > + * the necessary value > + */ > + val |= FIELD_PREP(PNV_OCXL_ATSD_AVA_AVA, addr >> (63-51)); > + out_be64(arva + PNV_OCXL_ATSD_AVA, val); > + } > + > + /* Write access initiates a shoot down to initiate the > + * TLB Invalidate command > + */ > + val = PNV_OCXL_ATSD_LNCH_R; > + val |= FIELD_PREP(PNV_OCXL_ATSD_LNCH_RIC, 0b10); > + if (addr) > + val |= FIELD_PREP(PNV_OCXL_ATSD_LNCH_IS, 0b00); > + else { > + val |= FIELD_PREP(PNV_OCXL_ATSD_LNCH_IS, 0b01); > + val |= PNV_OCXL_ATSD_LNCH_OCAPI_SINGLETON; > + } > + val |= PNV_OCXL_ATSD_LNCH_PRS; > + /* Actual Page Size to be invalidated > + * 000 4KB > + * 101 64KB > + * 001 2MB > + * 010 1GB > + */ > + size = 0b101; > + if (page_size == 0x1000) > + size = 0b000; > + if (page_size == 0x200000) > + size = 0b001; > + if (page_size == 0x40000000) > + size = 0b010; > + val |= FIELD_PREP(PNV_OCXL_ATSD_LNCH_AP, size); > + val |= FIELD_PREP(PNV_OCXL_ATSD_LNCH_PID, pid); > + out_be64(arva + PNV_OCXL_ATSD_LNCH, val); > + > + /* Poll the ATSD status register to determine when the > + * TLB Invalidate has been completed. > + */ > + val = in_be64(arva + PNV_OCXL_ATSD_STAT); > + pend = val >> 63; > + > + while (pend) { > + if (time_after_eq(jiffies, timeout)) { > + pr_err("%s - Timeout while reading XTS MMIO ATSD status register (val=%#llx, pidr=0x%lx)\n", > + __func__, val, pid); > + return; > + } > + cpu_relax(); > + val = in_be64(arva + PNV_OCXL_ATSD_STAT); > + pend = val >> 63; > + } > +} > +EXPORT_SYMBOL_GPL(pnv_ocxl_tlb_invalidate); >