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From: Juergen Schindele <schindele@nentec.de>
To: linuxppc-dev@lists.ozlabs.org
Subject: Freescale mpc8315 IRQ0 setup
Date: Mon, 10 Apr 2017 16:53:18 +0200	[thread overview]
Message-ID: <2666241.ms6yMRjznt@sherry> (raw)

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Dear mailing list,
i found out on our platform with freescale mpc8315 SOC that in
linux kernel code the setup of IRQ0 which we use is not correct.
One should be able to use falling EDGE interrupt capabilities like on
IRQ1-IRQ7. These setups are fixed in "arch/powerpc/sysdev/ipic.c"
The internal interrupt number of IRQ0 is not like IRQ1-IRQ7 in one block
but on number 48. To verify details please consult MPC8315ERM.pdf
developpers manual.

To correct these "EDGE" capabilities of IRQ0 i suggest the following 
patch:
please consider integrating it to your patches.

--- arch/powerpc/sysdev/ipic.c  (Revision correct)
+++ arch/powerpc/sysdev/ipic.c  (Arbeitskopie)
@@ -316,6 +316,7 @@
                .prio_mask = 7,
        },
        [48] = {
+               .ack    = IPIC_SEPNR,
                .mask   = IPIC_SEMSR,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SEFCR,

Thank you for your attention
-- 
i. A.
Jürgen Schindele
Softwareentwicklung

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             reply	other threads:[~2017-04-10 15:03 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-10 14:53 Juergen Schindele [this message]
2017-04-30  6:55 ` Freescale mpc8315 IRQ0 setup Scott Wood
2017-05-02 12:43   ` Juergen Schindele
2017-05-03  3:29     ` Scott Wood
2017-05-04 15:06       ` Juergen Schindele
2017-05-04 20:55         ` Scott Wood
2017-05-11 12:34           ` [PATCH] Freescale mpc8315 interrupt chip Juergen Schindele
2017-05-11 13:38             ` Oliver O'Halloran

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