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From: Kumar Gala <galak@kernel.crashing.org>
To: Nate Case <ncase@xes-inc.com>
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Subject: Re: [PATCH -next] powerpc/85xx: Add support for X-ES MPC85xx boards
Date: Mon, 8 Jun 2009 17:52:09 -0500
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On Jun 8, 2009, at 5:13 PM, Nate Case wrote:

> +static void xes_mpc85xx_configure_l1(void)
> +{
> +	uint spr;
> +	asm volatile("msync; isync");
> +	spr = mfspr(SPRN_L1CSR1);
> +	asm volatile("msync; isync");
> +	/* Enable instruction cache */
> +	mtspr(SPRN_L1CSR1, spr | L1CSR1_ICFI | L1CSR1_ICE | L1CSR1_CPE);
> +
> +	/* Enable L1 data cache if it isn't already enabled */
> +	if (mfspr(SPRN_L1CSR0) == 0x0) {
> +		printk(KERN_INFO "xes_mpc85xx: Enabling L1 caches\n");
> +		asm volatile("msync; isync");
> +		mtspr(SPRN_L1CSR0, 0x0);		/* Disable */
> +		asm volatile("msync; isync");
> +		mtspr(SPRN_L1CSR0, L1CSR0_DCFI);	/* Invalidate */
> +		asm volatile("msync; isync");
> +		spr = mfspr(SPRN_L1CSR0);
> +		asm volatile("msync; isync");
> +		mtspr(SPRN_L1CSR0, spr | L1CSR0_DCFI | L1CSR0_DCE |
> +				   L1CSR0_CPE);		/* Enable */
> +	}
> +}
> +

I'd prefer we move this into __setup_cpu_e500v1/__setup_cpu_e500v2 so  
its done for all processors regardless of platform.

- k