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Subject: RE: Regression detecting memory size on PPC440EPx
Date: Mon, 5 Oct 2009 12:23:16 -0400
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From: "Mike Nuss" <mike@terascala.com>
To: "Mikhail Zolotaryov" <lebon@lebon.org.ua>
Cc: linuxppc-dev@lists.ozlabs.org
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Mikhail Zolotaryov wrote:
> Hi Mike,
>=20
> you wrote:
> "Row address bits : 13
> DDR0_02 =3D 0x020C0E01
> DDR0_42 =3D 0x00000006"
>=20
> Register values above define that memory has 14 row address bits. The
> correct setting is (for CAS Latency =3D 3):
> DDR0_42 =3D 0x01000006
>=20
> Best regards,
> Mikhail Zolotaryov
>=20

Thank you! It was a bug in U-Boot (they were encoding that register
incorrectly). I'll submit a patch to them.

Mike