From: Kumar Gala <galak@kernel.crashing.org>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH 3/20] powerpc/mm: Add HW threads support to no_hash TLB management
Date: Thu, 30 Jul 2009 22:12:32 -0500 [thread overview]
Message-ID: <2E027F3C-8FAA-42EC-99B2-9B7EC470094E@kernel.crashing.org> (raw)
In-Reply-To: <20090724091523.8AD8CDDD1B@ozlabs.org>
On Jul 24, 2009, at 4:15 AM, Benjamin Herrenschmidt wrote:
> The current "no hash" MMU context management code is written with
> the assumption that one CPU == one TLB. This is not the case on
> implementations that support HW multithreading, where several
> linux CPUs can share the same TLB.
>
> This adds some basic support for this to our context management
> and our TLB flushing code.
>
> It also cleans up the optional debugging output a bit
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
I'm getting this nice oops on 32-bit book-e SMP (and I'm guessing its
because of this patch)
Unable to handle kernel paging request for data at address 0x00000000
Faulting instruction address: 0xc0016dac
Oops: Kernel access of bad area, sig: 11 [#1]
SMP NR_CPUS=8 MPC8572 DS
Modules linked in:
NIP: c0016dac LR: c0016d58 CTR: 0000001e
REGS: eed77ce0 TRAP: 0300 Not tainted (2.6.31-rc4-00442-gdb4c9c5)
MSR: 00021000 <ME,CE> CR: 24288482 XER: 20000000
DEAR: 00000000, ESR: 00000000
TASK = eecfe140[1581] 'msgctl08' THREAD: eed76000 CPU: 0
GPR00: 00400000 eed77d90 eecfe140 00000000 00000000 00000001 c05bf074
c05c0cf4
GPR08: 00000003 00000002 ff7fffff 00000000 00009b05 1004f894 c05bdd24
00000001
GPR16: ffffffff c05ab890 c05c0ce8 c04e0f58 c04da364 c05c0000 00000000
c04cfa04
GPR24: 00000002 00000000 00000000 c05c0cd8 00000080 00000000 ef056380
00000017
NIP [c0016dac] switch_mmu_context+0x15c/0x520
LR [c0016d58] switch_mmu_context+0x108/0x520
Call Trace:
[eed77d90] [c0016d58] switch_mmu_context+0x108/0x520 (unreliable)
[eed77df0] [c040efec] schedule+0x2bc/0x800
[eed77e70] [c01b9268] do_msgrcv+0x198/0x420
[eed77ef0] [c01b9520] sys_msgrcv+0x30/0xa0
[eed77f10] [c0003fe8] sys_ipc+0x1a8/0x2c0
[eed77f40] [c00116c4] ret_from_syscall+0x0/0x3c
Instruction dump:
57402834 7c00f850 3920fffe 5d2a003e 397b0010 5500103a 7ceb0214 60000000
60000000 81670000 39080001 38e70004 <7c0be82e> 7c005038 7c0be92e
81260000
---[ end trace 3c4c3106446e1bd8 ]---
- k
next prev parent reply other threads:[~2009-07-31 3:12 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-07-24 9:15 [PATCH 0/20] powerpc: base 64-bit Book3E processor support (v2) Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 1/20] powerpc/mm: Fix misplaced #endif in pgtable-ppc64-64k.h Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 2/20] powerpc/of: Remove useless register save/restore when calling OF back Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 3/20] powerpc/mm: Add HW threads support to no_hash TLB management Benjamin Herrenschmidt
2009-07-31 3:12 ` Kumar Gala [this message]
2009-07-31 3:35 ` Kumar Gala
2009-07-31 22:29 ` Benjamin Herrenschmidt
2009-08-03 2:03 ` Michael Ellerman
2009-08-03 16:21 ` Kumar Gala
2009-08-03 17:06 ` Dave Kleikamp
2009-08-03 17:57 ` Dave Kleikamp
2009-08-04 7:22 ` Benjamin Herrenschmidt
2009-08-03 21:03 ` Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 4/20] powerpc/mm: Add opcode definitions for tlbivax and tlbsrx Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 5/20] powerpc/mm: Add more bit definitions for Book3E MMU registers Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 6/20] powerpc/mm: Add support for early ioremap on non-hash 64-bit processors Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 7/20] powerpc: Modify some ppc_asm.h macros to accomodate 64-bits Book3E Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 8/20] powerpc/mm: Make low level TLB flush ops on BookE take additional args (v2) Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 9/20] powerpc/mm: Call mmu_context_init() from ppc64 (v2) Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 10/20] powerpc: Clean ifdef usage in copy_thread() Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 11/20] powerpc: Move definitions of secondary CPU spinloop to header file (v2) Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 12/20] powerpc/mm: Rework & cleanup page table freeing code path Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 13/20] powerpc: Add SPR definitions for new 64-bit BookE (v2) Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 14/20] powerpc: Add memory management headers " Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 15/20] powerpc: Add definitions used by exception handling on 64-bit Book3E (v2) Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 16/20] powerpc: Add PACA fields specific to 64-bit Book3E processors Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 17/20] powerpc/mm: Move around mmu_gathers definition on 64-bit (v2) Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 18/20] powerpc: Add TLB management code for 64-bit Book3E (v2) Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 19/20] powerpc/mm: Add support for SPARSEMEM_VMEMMAP on 64-bit Book3E Benjamin Herrenschmidt
2009-07-24 9:15 ` [PATCH 20/20] powerpc: Remaining 64-bit Book3E support (v2) Benjamin Herrenschmidt
-- strict thread matches above, loose matches on Subject: below --
2009-07-23 5:59 [PATCH 3/20] powerpc/mm: Add HW threads support to no_hash TLB management Benjamin Herrenschmidt
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