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From: Segher Boessenkool <segher@kernel.crashing.org>
Subject: Re: [PATCH 1/5] powerpc/85xx: issue 15 EOI after core reset for FSL
 CoreNet devices
Date: Wed, 26 Oct 2011 20:30:04 +0200
To: Matthew McClintock <msm@freescale.com>
Cc: kumar.gala@freescale.com, linuxppc-dev@lists.ozlabs.org
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> @@ -1759,6 +1760,12 @@ void mpic_reset_core(int cpu)
>  	pir &= ~(1 << cpuid);
>  	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
>  	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
> +
> +	/* Perform 15 EOI on each reset core to clear pending interrupts */
> +	for (i = 0; i < 15; i++) {
> +		_mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
> +				      MPIC_CPU_EOI, 0);
> +	}

This is generic code, right?  Please add info to the comment about
which devices need this quirk, then.


Segher