From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from wf-out-1314.google.com (wf-out-1314.google.com [209.85.200.168]) by ozlabs.org (Postfix) with ESMTP id 825F1DDE06 for ; Tue, 31 Mar 2009 21:58:35 +1100 (EST) Received: by wf-out-1314.google.com with SMTP id 24so2802267wfg.15 for ; Tue, 31 Mar 2009 03:58:33 -0700 (PDT) MIME-Version: 1.0 Sender: pku.leo@gmail.com In-Reply-To: References: <1238089445-28396-1-git-send-email-Joakim.Tjernlund@transmode.se> <49CCD3E8.9040007@freescale.com> <49D0FFBB.7000009@freescale.com> <49D1052D.2050609@freescale.com> <49D11E47.8080106@freescale.com> Date: Tue, 31 Mar 2009 18:58:33 +0800 Message-ID: <2a27d3730903310358t56caaba9uba6e1835b716bc25@mail.gmail.com> Subject: Re: [PATCH] ucc_geth: Rework the TX logic. From: Li Yang To: Joakim Tjernlund Content-Type: text/plain; charset=UTF-8 Cc: Scott Wood , linuxppc-dev@ozlabs.org, netdev@vger.kernel.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, Mar 31, 2009 at 5:07 PM, Joakim Tjernlund wrote: > Scott Wood wrote on 30/03/2009 21:32:23: >> >> Joakim Tjernlund wrote: >> >> different since descriptors are in MURAM which is ioremap()ed -- > though >> >> switching to a cacheable mapping with barriers should be a > performance >> >> improvement. >> > >> > I always thought that MURAM was very fast. The whole reason to have > BDs in >> > MURAM is that it is faster than normal RAM, at least that is what I >> > thought. >> >> Yeah, on second thought it probably wouldn't be worth it. =C2=A0There's = also >> the question of under what circumstances the QE's MURAM accesses will be > >> cache-coherent. > > I am a bit confused, what isn't worth it? Currently MURAM isn't used by > ucc_geth, but > it is easy to change. Swap MEM_PART_SYSTEM to MEM_PART_MURAM, however, > just > tried that and the driver stopped working. I known this worked earlier > because > I tried it and I even think I sent a patch to Leo. > > What choices do we have, I see three: > > 1) MEM_PART_SYSTEM, as today. > 2) MEM_PART_MURAM. I guess this should be uncacheable memory? > 3) as gianfar, dma_alloc_coherent(). I presume this is uncacheable memory= ? > 1 and 3 are the same. All of them use cacheable memory as we have a hardware coherency module to take care of the cache coherency problem. However it might be better to use dma_alloc_coherent() for the code to be more readible. Thanks. - Leo