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charset="UTF-8" User-Agent: Evolution 3.34.4 (3.34.4-1.fc31) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Hello Alexey, thank you for this feedback! On Sat, 2020-08-22 at 19:33 +1000, Alexey Kardashevskiy wrote: > > +#define TCE_RPN_BITS 52 /* Bits 0-51 represent RPN on TCE */ > > Ditch this one and use MAX_PHYSMEM_BITS instead? I am pretty sure this > is the actual limit. I understand this MAX_PHYSMEM_BITS(51) comes from the maximum physical memory addressable in the machine. IIUC, it means we can access physical address up to (1ul << MAX_PHYSMEM_BITS). This 52 comes from PAPR "Table 9. TCE Definition" which defines bits 0-51 as the RPN. By looking at code, I understand that it means we may input any address < (1ul << 52) to TCE. In practice, MAX_PHYSMEM_BITS should be enough as of today, because I suppose we can't ever pass a physical page address over (1ul << 51), and TCE accepts up to (1ul << 52). But if we ever increase MAX_PHYSMEM_BITS, it doesn't necessarily means that TCE_RPN_BITS will also be increased, so I think they are independent values. Does it make sense? Please let me know if I am missing something. > > > > +#define TCE_RPN_MASK(ps) ((1ul << (TCE_RPN_BITS - (ps))) - 1) > > #define TCE_VALID 0x800 /* TCE valid */ > > #define TCE_ALLIO 0x400 /* TCE valid for all lpars */ > > #define TCE_PCI_WRITE 0x2 /* write from PCI allowed */ > > diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c > > index e4198700ed1a..8fe23b7dff3a 100644 > > --- a/arch/powerpc/platforms/pseries/iommu.c > > +++ b/arch/powerpc/platforms/pseries/iommu.c > > @@ -107,6 +107,9 @@ static int tce_build_pSeries(struct iommu_table *tbl, long index, > > u64 proto_tce; > > __be64 *tcep; > > u64 rpn; > > + const unsigned long tceshift = tbl->it_page_shift; > > + const unsigned long pagesize = IOMMU_PAGE_SIZE(tbl); > > + const u64 rpn_mask = TCE_RPN_MASK(tceshift); > > Using IOMMU_PAGE_SIZE macro for the page size and not using > IOMMU_PAGE_MASK for the mask - this incosistency makes my small brain > explode :) I understand the history but maaaaan... Oh well, ok. > Yeah, it feels kind of weird after two IOMMU related consts. :) But sure IOMMU_PAGE_MASK() would not be useful here :) And this kind of let me thinking: > > + rpn = __pa(uaddr) >> tceshift; > > + *tcep = cpu_to_be64(proto_tce | (rpn & rpn_mask) << tceshift); Why not: rpn_mask = TCE_RPN_MASK(tceshift) << tceshift; rpn = __pa(uaddr) & rpn_mask; *tcep = cpu_to_be64(proto_tce | rpn) I am usually afraid of changing stuff like this, but I think it's safe. > Good, otherwise. Thanks, Thank you for reviewing!