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Wed, 20 May 2026 00:27:22 +0800 (CST) Message-ID: <3464ded9-721a-4eb2-afb6-bbca6fdc8a46@163.com> Date: Wed, 20 May 2026 00:27:21 +0800 X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/3] PCI: dwc: Cache PCIe capability offset and simplify drivers To: Manivannan Sadhasivam Cc: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, jingoohan1@gmail.com, mx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260509135152.2241235-1-18255117159@163.com> <5cc6fbcc-98eb-4da5-b123-2c04c4d39326@163.com> Content-Language: en-US From: Hans Zhang <18255117159@163.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CM-TRANSID:_____wDXEFBpjwxq6iYtCQ--.55083S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxJr47Gw4rWF47AFy3tr43Jrb_yoW8uryfpa y3JF1Syr48XF4fXan2va1rZF4xt3ZxArWUZ395Cryavr9I9Fy3JrsY9ryYkF9rCFs2yr15 uF4Yqry29r15AaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRiiSJUUUUU= X-Originating-IP: [240e:b8f:91b3:d000:9130:b3d8:6241:39fd] X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAubP2oMj2sFdQAA3Z On 5/20/26 00:15, Manivannan Sadhasivam wrote: > On Wed, May 20, 2026 at 12:09:28AM +0800, Hans Zhang wrote: >> >> >> On 5/19/26 21:57, Manivannan Sadhasivam wrote: >>> On Sat, May 09, 2026 at 09:51:49PM +0800, Hans Zhang wrote: >>>> The DWC PCIe core and its many platform drivers repeatedly call >>>> dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) to obtain the offset of the >>>> PCI Express Capability structure. This is wasteful and makes the code >>>> verbose. And some even search for the PCI_CAP_ID_EXP offset value within >>>> the suspend/resume functions. >>>> >>> >>> Sashiko has flagged some real issues with this series in accessing DBI space >>> very early and 'pci->pcie_cap' being 0. >> >> >> Hi Mani, >> >> We have discussed this issue in the Cadence driver. I think it won't cause >> any problems. Specifically as follows: >> >> https://lore.kernel.org/linux-pci/5823faec-d972-4c77-90ec-a215c686e0a8@163.com/ >> """ >> As per PCIe r7.0, sec 7.5.1.1.11, Since all PCI Express Functions are >> required to implement the PCI Express Capability structure, which >> must be included somewhere in this linked list. >> """ >> >> >> >> Bjorn also responded as follows: >> https://lore.kernel.org/linux-pci/20260505212306.GA744158@bhelgaas/ >> """ >> It's true that all Root Ports must have a PCIe Capability. >> """ >> > > Ok, what about reading the DBI registers very early? Hi Mani, Yes. I have performed the DBI read register operation at the very beginning of the following code. dw_pcie_ep_init() dw_pcie_get_pcie_cap(pci); dw_pcie_host_init dw_pcie_get_pcie_cap(pci); However, for some glue drivers, they need to configure the registers of the PCIe Express Capability earlier than calling dw_pcie_host_init()/dw_pcie_ep_init(). So, for example, in the file: drivers/pci/controller/dwc/pcie-tegra194.c. Here, it is necessary to find the value of 'pci->pcie_cap' earlier. Then, dw_pcie_host_init()/dw_pcie_ep_init() will no longer search for the offset value of the PCIe Express Capability. Best regards, Hans