From: Dan Malek <dmalek@jlc.net>
To: Cort Dougan <cort@persephone.cs.nmt.edu>
Cc: Paul Mackerras <paulus@cs.anu.edu.au>,
Geert Uytterhoeven <Geert.Uytterhoeven@cs.kuleuven.ac.be>,
bh40@calva.net, tmrini@ntplx.net,
linuxppc-dev@lists.linuxppc.org
Subject: Re: irq cleanup
Date: Sun, 03 Jan 1999 20:37:39 -0500 [thread overview]
Message-ID: <36901B63.5F905878@jlc.net> (raw)
In-Reply-To: Pine.LNX.3.96.981231143743.14310A-100000@persephone.cs.nmt.edu
Cort Dougan wrote:
> I was adding code for the QSPAN interrupts on the mbx.....
I am a little confused by this. I am travelling and don't have
my books handy. and I remember the MBX uses the 8259
interrupt controller to manage all PCI/ISA device interrupts.
What I don't remember are the actual connections. I believe
the PCI interrupts are routed to the 8259, which is then
routed to one of the 8xx external interrupts.
The QSPAN interrupts are for things like PCI parity
errors and the IDMA. However, the IDMA won't operate
because of a silicon bug that will not allow the QSPAN to
be a master on the 8xx bus.
To support PCI or ISA devices that interrupt on the MBX
you would need to modify irq.c to support a multilevel interrupt
scheme. The 8259 would interrupt on one of the 8xx interrupt
controller levels, then you would have to process all 8259
interrupts.
> The idea is to have a master controller, and each slave is dealt with as a
> handler so we don't have such an ifdef soup.
That's the right idea. The master in this case would
be the 8xx interrupt controller, and the slave would be the 8259.
The QSpan isn't part of the picture.
-- Dan
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next prev parent reply other threads:[~1999-01-04 1:37 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
1998-12-31 21:43 irq cleanup Cort Dougan
1999-01-04 1:37 ` Dan Malek [this message]
1999-01-05 1:48 ` Cort Dougan
1999-01-05 5:33 ` Dan Malek
1999-01-05 9:05 ` Geert Uytterhoeven
1999-01-05 21:06 ` Cort Dougan
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