* irq cleanup
@ 1998-12-31 21:43 Cort Dougan
1999-01-04 1:37 ` Dan Malek
0 siblings, 1 reply; 6+ messages in thread
From: Cort Dougan @ 1998-12-31 21:43 UTC (permalink / raw)
To: Paul Mackerras, Dan Malek, Geert Uytterhoeven, bh40, tmrini; +Cc: linuxppc-dev
I was adding code for the QSPAN interrupts on the mbx when I decided it
would take as much work to hack it in as to redesign irq.c. This isn't
done, but I wanted to show you what direction I was going in and get
some feedback on it. I'm basing it on the Ingo design a bit but with some
changes so it's a better match with the ppc hardware.
This will also help with adding the yellowknife when I get a chance to
start on that.
The idea is to have a master controller, and each slave is dealt with as a
handler so we don't have such an ifdef soup.
I have it going on the powerbook now. I'll test it out on chrp and prep
next then finish up the qspan stuff.
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: irq cleanup
1998-12-31 21:43 irq cleanup Cort Dougan
@ 1999-01-04 1:37 ` Dan Malek
1999-01-05 1:48 ` Cort Dougan
0 siblings, 1 reply; 6+ messages in thread
From: Dan Malek @ 1999-01-04 1:37 UTC (permalink / raw)
To: Cort Dougan
Cc: Paul Mackerras, Geert Uytterhoeven, bh40, tmrini, linuxppc-dev
Cort Dougan wrote:
> I was adding code for the QSPAN interrupts on the mbx.....
I am a little confused by this. I am travelling and don't have
my books handy. and I remember the MBX uses the 8259
interrupt controller to manage all PCI/ISA device interrupts.
What I don't remember are the actual connections. I believe
the PCI interrupts are routed to the 8259, which is then
routed to one of the 8xx external interrupts.
The QSPAN interrupts are for things like PCI parity
errors and the IDMA. However, the IDMA won't operate
because of a silicon bug that will not allow the QSPAN to
be a master on the 8xx bus.
To support PCI or ISA devices that interrupt on the MBX
you would need to modify irq.c to support a multilevel interrupt
scheme. The 8259 would interrupt on one of the 8xx interrupt
controller levels, then you would have to process all 8259
interrupts.
> The idea is to have a master controller, and each slave is dealt with as a
> handler so we don't have such an ifdef soup.
That's the right idea. The master in this case would
be the 8xx interrupt controller, and the slave would be the 8259.
The QSpan isn't part of the picture.
-- Dan
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: irq cleanup
1999-01-04 1:37 ` Dan Malek
@ 1999-01-05 1:48 ` Cort Dougan
1999-01-05 5:33 ` Dan Malek
0 siblings, 1 reply; 6+ messages in thread
From: Cort Dougan @ 1999-01-05 1:48 UTC (permalink / raw)
To: Dan Malek; +Cc: Paul Mackerras, Geert Uytterhoeven, bh40, tmrini, linuxppc-dev
Right, the winbond has a couple 8259's emulated on it. They're routed to
irq 3 on the 8xx.
}I am a little confused by this. I am travelling and don't have
}my books handy. and I remember the MBX uses the 8259
}interrupt controller to manage all PCI/ISA device interrupts.
}What I don't remember are the actual connections. I believe
}the PCI interrupts are routed to the 8259, which is then
}routed to one of the 8xx external interrupts.
I think some devices can be routed through the qspan as well. The docs I
have are not clear.
}The QSPAN interrupts are for things like PCI parity
Right, that's the plan.
}To support PCI or ISA devices that interrupt on the MBX
}you would need to modify irq.c to support a multilevel interrupt
}scheme. The 8259 would interrupt on one of the 8xx interrupt
}controller levels, then you would have to process all 8259
}interrupts.
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: irq cleanup
1999-01-05 1:48 ` Cort Dougan
@ 1999-01-05 5:33 ` Dan Malek
1999-01-05 9:05 ` Geert Uytterhoeven
0 siblings, 1 reply; 6+ messages in thread
From: Dan Malek @ 1999-01-05 5:33 UTC (permalink / raw)
To: Cort Dougan
Cc: Paul Mackerras, Geert Uytterhoeven, bh40, tmrini, linuxppc-dev
Cort Dougan wrote:
> Right, that's the plan.
>
> }To support PCI or ISA devices that interrupt on the MBX
> }you would need to modify irq.c to support a multilevel interrupt
> }scheme. The 8259 would interrupt on one of the 8xx interrupt
> }controller levels, then you would have to process all 8259
> }interrupts.
Are there other systems designed like this with a multilevel
interrupt controller? It's not hard to imagine, although I have
never seen one before the MBX. This is one reason I didn't
spend any effort when I did the iniitial port. It seemed like
lots of work for a single board not likely to use them
-- Dan
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: irq cleanup
1999-01-05 5:33 ` Dan Malek
@ 1999-01-05 9:05 ` Geert Uytterhoeven
1999-01-05 21:06 ` Cort Dougan
0 siblings, 1 reply; 6+ messages in thread
From: Geert Uytterhoeven @ 1999-01-05 9:05 UTC (permalink / raw)
To: Dan Malek; +Cc: Cort Dougan, Paul Mackerras, bh40, tmrini, linuxppc-dev
On Tue, 5 Jan 1999, Dan Malek wrote:
> Cort Dougan wrote:
> > Right, that's the plan.
> >
> > }To support PCI or ISA devices that interrupt on the MBX
> > }you would need to modify irq.c to support a multilevel interrupt
> > }scheme. The 8259 would interrupt on one of the 8xx interrupt
> > }controller levels, then you would have to process all 8259
> > }interrupts.
>
> Are there other systems designed like this with a multilevel
> interrupt controller? It's not hard to imagine, although I have
> never seen one before the MBX. This is one reason I didn't
> spend any effort when I did the iniitial port. It seemed like
> lots of work for a single board not likely to use them
LongTrail CHRP has the output of the master i8259 routed through the OpenPIC.
So it has 3 interrupt controllers:
- irq 0-7: master i8259 -> irq 16
- irq 8-15: slave i8259 -> irq 2
- irq 16-35: OpenPIC in Hydra -> CPU
Greetings,
Geert
--
Geert Uytterhoeven Geert.Uytterhoeven@cs.kuleuven.ac.be
Wavelets, Linux/{m68k~Amiga,PPC~CHRP} http://www.cs.kuleuven.ac.be/~geert/
Department of Computer Science -- Katholieke Universiteit Leuven -- Belgium
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: irq cleanup
1999-01-05 9:05 ` Geert Uytterhoeven
@ 1999-01-05 21:06 ` Cort Dougan
0 siblings, 0 replies; 6+ messages in thread
From: Cort Dougan @ 1999-01-05 21:06 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Dan Malek, Paul Mackerras, bh40, tmrini, linuxppc-dev
Yelloknife has the same thing, but backwards. That's jumper switchable
though.
}LongTrail CHRP has the output of the master i8259 routed through the OpenPIC.
}So it has 3 interrupt controllers:
}
} - irq 0-7: master i8259 -> irq 16
} - irq 8-15: slave i8259 -> irq 2
} - irq 16-35: OpenPIC in Hydra -> CPU
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~1999-01-05 21:06 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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1998-12-31 21:43 irq cleanup Cort Dougan
1999-01-04 1:37 ` Dan Malek
1999-01-05 1:48 ` Cort Dougan
1999-01-05 5:33 ` Dan Malek
1999-01-05 9:05 ` Geert Uytterhoeven
1999-01-05 21:06 ` Cort Dougan
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