From: Dan Malek <dmalek@jlc.net>
To: Cort Dougan <cort@persephone.cs.nmt.edu>
Cc: Paul Mackerras <paulus@cs.anu.edu.au>,
Geert Uytterhoeven <Geert.Uytterhoeven@cs.kuleuven.ac.be>,
bh40@calva.net, tmrini@ntplx.net,
linuxppc-dev@lists.linuxppc.org
Subject: Re: irq cleanup
Date: Tue, 05 Jan 1999 00:33:15 -0500 [thread overview]
Message-ID: <3691A41B.5BB09E15@jlc.net> (raw)
In-Reply-To: Pine.LNX.3.96.990104184703.27992A-100000@persephone.cs.nmt.edu
Cort Dougan wrote:
> Right, that's the plan.
>
> }To support PCI or ISA devices that interrupt on the MBX
> }you would need to modify irq.c to support a multilevel interrupt
> }scheme. The 8259 would interrupt on one of the 8xx interrupt
> }controller levels, then you would have to process all 8259
> }interrupts.
Are there other systems designed like this with a multilevel
interrupt controller? It's not hard to imagine, although I have
never seen one before the MBX. This is one reason I didn't
spend any effort when I did the iniitial port. It seemed like
lots of work for a single board not likely to use them
-- Dan
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next prev parent reply other threads:[~1999-01-05 5:33 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
1998-12-31 21:43 irq cleanup Cort Dougan
1999-01-04 1:37 ` Dan Malek
1999-01-05 1:48 ` Cort Dougan
1999-01-05 5:33 ` Dan Malek [this message]
1999-01-05 9:05 ` Geert Uytterhoeven
1999-01-05 21:06 ` Cort Dougan
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