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Subject: Re: [PATCH] powerpc: Fix xmon for systems without MSR[RI]
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From: Jimi Xenidis <jimix@pobox.com>
In-Reply-To: <4E5D272B.6000403@freescale.com>
Date: Wed, 31 Aug 2011 16:08:48 -0500
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	<1314684670.2488.82.camel@pasglop> <4E5D272B.6000403@freescale.com>
To: Scott Wood <scottwood@freescale.com>
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On Aug 30, 2011, at 1:08 PM, Scott Wood wrote:

> On 08/30/2011 01:11 AM, Benjamin Herrenschmidt wrote:
>> On Mon, 2011-08-08 at 16:25 -0500, Jimi Xenidis wrote:
>>> From: David Gibson <dwg@au1.ibm.com>
>>>=20
>>> Based on patch by David Gibson <dwg@au1.ibm.com>
>>>=20
>>> xmon has a longstanding bug on systems which are SMP-capable but =
lack
>>> the MSR[RI] bit.  In these cases, xmon invoked by IPI on secondary
>>> CPUs will not properly keep quiet, but will print stuff, thereby
>>> garbling the primary xmon's output.  This patch fixes it, by =
ignoring
>>> the RI bit if the processor does not support it.
>>>=20
>>> There's already a version of this for 4xx upstream, which we'll need
>>> to extend to other RI-lacking CPUs at some point.  For now this adds
>>> BookE processors to the mix.
>>=20
>> Don't freescale one have RI ?
>=20
> e500mc does.

hmm, according to the ISA, MSR[RI] is only defined for Book3s and is not =
defined for Book3e
Should we scope it to just book3e?
-jx

>=20
> e500v2 doesn't -- if a machine check happens while MSR[ME]=3D0, it =
causes
> a checkstop.
>=20
> -Scott
>=20